Hardware - Computer Architecture Flashcards

1
Q

what is the role of the CPU in a computer

A

continuously processes instructions and data that are inputted by repeatedly carrying out the fetch-execute cycle in order to output a result

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2
Q

what is meant by a microprocessor

A

a type of integrated circuit on a single chip that processes instruction

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3
Q

what are the 5 key elements of Von Neumann architecture:

A
  • data + instruction are both stored as binary digits
  • data + instructions both stored in primary memory
  • instructions are fetched one at a time and in order (sequentially)
  • cycle continues until no more instructions are available
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4
Q

what components are in the CPU

A
  • ALU (Arithmetic Logic Unit)
  • Control Unit
  • Clock
  • Registers
  • Address, Data and Control Buses
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5
Q

what is the function of the ALU

A
  • carries out mathematical + logical operations on data, including:
    • Mathematical = ADD, SUBSTRACT
    • binary shifts
    • Logical = AND, OR , NOT
    • compares values held in registers
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6
Q

what is the function of the accumulator (ACC)

A
  • register in which results of operations carried out in the ALU are ** temporarily stored** for quicker retrieval
  • one of several general-purpose registers
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7
Q

what components are in the ALU units

A
  • MDR
  • ACC
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8
Q

function of the CU

A
  • coordinates all of the CPU’s actions in the fetch-decode-execute cycle and decodes instruction
  • sends + receives control signals to fetch + write data
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9
Q

what is the function of the Clock

A
  • Electronic unit that synchronises + regulates the speed and timings of all signals + computer functions
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10
Q

what is the function of Registers

A
  • very small, very fast memory locations
  • registers built into the CPU chip to temporarily store memory addresses, instructions or data
  • used in the fetch-decode-execute cycle for specific purposes
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11
Q

what does PC stand for

A

Program Counter

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12
Q

what is the function of the Program Counter

A
  • is a register that golds the memory address of the next instruction to be processed
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13
Q

what is MAR

A

Memory Address Register

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14
Q

what is the function of the MAR

A
  • holds address (location in memory) of the current instruction / piece of data to be fetched or stored
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15
Q

to which component does the MAR send the address to

A

to the main memory down the *address bus**

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16
Q

what does MDR stand for

A

Memory Data Register

17
Q

what is the function of the MDR

A
  • temporarily holds data / program instruction when it is:
    • fetched from memory OR
    • data the is waiting to be written to memory
18
Q

what must all data do when travelling to and from the main memory

A

travel down the Data Bus and pass through the MDR

19
Q

what does CIR stand for

A

Current Instruction Register

20
Q

what is the function of the CIR

A
  • holds the instruction hat is currently being executed
  • if MDR contains an instruction, this will be copied to the CIR
21
Q

what are the 3 types of buses

A
  • address
  • data
  • control
22
Q

what is the purpose of an address bus

A

Unidirectional - carries memory addresses that identify where data is being read from or written to

23
Q

what is the purpose of an data bus

A

Bidirectional - carries the binary 1s and 0s that make up the actual information being transmitted around the CPU / computer

24
Q

what is the purpose of an control bus

A

Bidirectional - carries command + control signals to and from one component to another in the CPU

25
what is the fetch-decode-execute cycle
- **continuous repetitive cycle** - every CPU instruction is **fetched from memory** - is then **decoded** by the **Control Unit** to find out what to do with it - instruction is then **executed**
26
each operation carried out within the fetch-decode-execute cycle is regulated by what
a 'tick' or **cycle** of the **CPU clock**
27
describe in detail the stages of the fetch-decode-execute cycle
FETCH Stage: 1. The memory **address** held in the **program counter** is **copied** into the **MAR** 2. **increment PC** so that **address** is now for the **next instruction** can be fetched 3. processer sends **signal** to address in **MAR** to be sent along **address bus** to *main memory** --> where it **waits** to receive a **signal** from the **control bus** 4. CU sends a **read signal** along **control bus** to main memory 5. contents at address within memory is sent along the **data bus** and to the **MDR** 6. data received in MDR is **copied to Current Instruction Register** 7. data in CIR is **decoded + executed** --> results of processing are **stored** in the **ACC** 8. repeats
28
what components are in the CU
- PC - CIR - MAR
29
describe the steps within the Decode stage
- instruction held in **CIR** is inspected and **decoded** to work out what needs to be done
30
describe the steps within the Execute stage
- send **address** from CIR to **MAR** - send data down the **address bus** to **main memory** for it to **read** --> **CU** sends **read signal** along **control bus** to main memory - address sent along **data bus** to **MDR** - contents of MDR are **copied** to the **ACC** to be carried out