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Tech > Hardware > Flashcards

Hardware Flashcards

1
Q

RME: definition and one thing

A

Realm management extension
Architecture extension for Arm’s confidential compute architecture

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2
Q

SME

A

Scalable matrix extension

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3
Q

ICC_IAR

A

Interrupt acknowledge register

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4
Q

MTE: How do enable tag checking for a memory region in stage 1?

A

PTE index to MAIR with tagged attribute

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5
Q

What’s WIMG?

A

Memory attributes in pmap such as cache abilities and MTE

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6
Q

POE2

A

Permissions overlay extension 2

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7
Q

MTE: tag to memory ratio

A

4 bit tag for every 16 bytes of physical memory

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8
Q

MTE: read, write and generate tag instructions

A

LDG, STG, IRG

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9
Q

AMX

A

Apple matrix extension

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10
Q

CPMU: definition and four features

A

Core performance monitor unit
Cycle counter
Filtered event counter
Event sampling
Counter overflow exception

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11
Q

UPMU: definition and its two features

A

Uncore performance monitor unit
Counting events in uncore blocks such as LLC
counter overflow exception

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12
Q

CLPC: definition, description, aka

A

Closed loop performance control
System power management and performance control
Also known as AON_PMU

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13
Q

H16 Mac Chips

A

G: Donan
Brava

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14
Q

H17 Mac Chips

A

G: Hydra
Sotra

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15
Q

H18 Mac Chips

A

P: Thera
A: Tilo
G: Komodo

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16
Q

Apple silicon high density compute server 2025: code, chip, storage, NIC, ancestor

A

J226
Replaces J126
32x H17G
1 TB storage
200 Gbps NIC

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17
Q

HDR: definition and description

A

High dynamic range
Enable a monitor to display a broader spectrum of colors and contrasts

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18
Q

ARM system ready

A

Measures compliance to a set of hardware and firmware standards

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19
Q

GICH_ELRSR: description

A

Empty list register status register

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20
Q

AVX

A

Advanced vector extension

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21
Q

CPP RCTX

A

Cache prefetch prediction restriction by context

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22
Q

CFP RCTX

A

Control flow prediction restriction by context

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23
Q

ARM： FEAT_LOR - definition and description

A

Limited ordering regions
Allow large systems to perform special load and store instructions that provide order for a specified region of physical memory

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24
Q

POE: how to identify code and data spatially

A

Translation of the VA on a per page granularity

25
Q

POE: how to identify code temporally

A

TIndex

26
Q

POE: 3 spatial access enforcement

A

What code can read or write what data
What code can branch or return to what other code
What code can execute which instructions or access which system registers

27
Q

POE: POIndex: definition and description

A

Permission overlay index
Specified in stage 1 translation table descriptor

28
Q

POE: FPOIndex: definition and description

A

Fetch POIndex
The POIndex from the translation of current PC VA

29
Q

POE: DPOIndex: definition and description

A

Data POIndex
The POIndex from the translation of the VA for the target of a memory accessing instruction

30
Q

POE: TIndex

A

Temporal index

31
Q

POE: POTIndex: definition and description

A

Permission overlay table index
Index into DPOT and TTT

32
Q

POE: FGDTIndex: definition and description

A

Fine grained dynamic trap index
Select which FGDT register to use

33
Q

POE: IRT: definition, 2 input, 3 output

A

Instruction region table
In memory table that generates execute permission, FGDTIndex and POTIndex from TIndex and FPOIndex

34
Q

POE: DPOT: definition and description

A

Data permission overlay table
Describes stage 1 data read and write permission subtractions from POTIndex and DPOIndex

35
Q

POE: TTT: definition and description

A

TIndex transition table
Describe the permitted transitions of TIndex

36
Q

POE: FGDT: definition and description

A

Fine grained dynamic trap
Restrict instruction and system register accesses

37
Q

POE: PLB

A

Permission look aside buffer

38
Q

POE: LDSTT_ELx

A

Value of FPOIndex to be used by load and store unprivileged instructions

39
Q

POE: TPS: D2

A

Thread private state check
Restrict any access by the thread to a thread private page that is outside its min and max bounds

40
Q

RDMA: d2

A

Remote direct memory access
Access from the memory of one computer into that of another without involving either one’s operating system

41
Q

Context synchronization event: what, how 3

A

Guarantee visibility of any system register change
ISB
exception entry and return
Exit from debug state

42
Q

ARM: S2PIE: definition

A

Stage 2 Permission Indirection Enable

43
Q

ARM: TPS: d2

A

Thread private state
Prevent access to a thread private page that is outside its min and max bounds

44
Q

ARM: BTI2: where, three requirements

A

Enhanced guarded page
Link register set by instruction before BTI c
landing pad for branches
landing pad for returns

45
Q

ARM Memory: Uncached: what and when

A

Provides real time guarantees as the memory is never cached
Available in H12+

46
Q

ARM memory: non cached

A

Write combined memory that reduces likelihood of cache snooping

47
Q

RGSR_EL1

A

Random (allocation tag) generator seed register

48
Q

GCR_EL1

A

Tag control register

49
Q

TFSR_EL1

A

Tag fault status register

50
Q

VMSA Locks

A

Control the MSR write-access to various ARM ISA system registers.

51
Q

APRR: definition

A

Access protection restriction register

52
Q

Granule protection table

A

Tracks whether a page is used for realms, trust zone or normal world

53
Q

H19 SoC Names

A

P/iPhone: Borneo
A/iPhone: Banda
ASM: Andros
G: Delos

54
Q

ISA: TUNIMP

A

Trap unimplemented PSTATE or instructions

55
Q

FEAT_NV2p1

A

Retain bits that are used in EL2 but reserved in EL1

56
Q

FEAT_ECV: what, 2 benefits for our virtualization stack

A

Enhanced counter virtualization
offset between EL0/1 and EL2 view of physical time
Direct physical timer interrupt to vGIC

57
Q

FEAT_UINJ

A

Provide higher privilege software with a future proofed mechanism to inject an Undefined Instruction exception into lower privilege software

58
Q

S1PIE

A

Arm indirection permission scheme

Tech (5 decks)

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