ARM GICv3 Flashcards
Two Purposes
Distributor
GICv3
Interrupt prioritization
Distribution of SPIs and SGIs to the PEs
configuration
Redistributor
GICv3
Provides configuration settings for PPIs, SGIs and LPIs
When is interrupt 1023 received?
GICv3
In response to interrupt acknowledge when no appropriate pending interrupt
Description, Where
Affinity Routing
GICv3
Hierarchical address-based scheme to identify specific PE nodes for interrupt routing
Defined in MPIDR_EL1
Two ways
How are SPIs routed?
GICv3
Specific PE or any one PE
Two ways
Who can receive SGIs?
GICv3
All participating PEs except self or specific set of PEs in a cluster
Four logical components
GICv3
A distributor
A redistributor for each PE
A CPU interface for each PE
Interrupt Translation Service
Which components
LPI Routing
GICv3
Optional via ITS
Redistributor
CPU interface
Which components
PPI Routing
GICv3
Redistributor
CPU interface
Which components
SPI Routing
GICv3
Distributor
Redistributor
CPU interface
Which components
SGI Routing
GICv3
Source CPU interface
Source Redistributor
Distributor
Redistributor
CPU interface
3 for each interrupt , 3 for all, 1 for pending
Seven functions of CPU programming interface
GICv3
Enabling interrupt handling
Acknowledging an interrupt.
Performing a priority drop.
Deactivation of an interrupt.
Setting an interrupt priority mask for the PE.
Defining the preemption policy for the PE.
Determining the highest priority pending interrupt for the PE.
Three components of CPU interface
GICv3
ICC: Supervisor to control physical interrupts
ICV: Superivsor to control virtual interrupts
ICH: Hypervisor to control pending interrupts
Six steps of interrupt lifecycle
GICv3
Generate
Distribute to CPU interface
Deliver to PE
Activate
Priority Drop
Deactivation
Idle Priority
GICv3
Running priority when no interrupts are active
Which interrupt identifiers are local to a PE
GICv3
PPI and SGI
Which interrupt identifiers are global
GICv3
SPI and LPI
Desciption, variation, PCIe
Message-based interrupt
GICv3
Interrupt from memory write
SPI or LPI
MSI and MSI-X for PCIe
Two situations
Running priority
GICv3
Group priority of the highest priority active interrupt that didn’t get priority drop
Or idle priority
Maintenance Interrupt
GICv3
A physical interrupt that signals key events associated with interrupt handling on a VM
When is edge-triggered interrupt active?
GICv3
Another edge has not been detected since the interrupt is acknowledged
When is level-trigged interrupt active?
GICv3
The level has been deasserted since the interrupt was acknowledged.
When is edge-triggered interrupt active and pending?
GICv3
Another edge has been detected since the interrupt was acknowledged.
When is a level-triggered interrupt active and pending?
GICv3
The level has not been deasserted since the interrupt was acknowledged.
Purpose
Group Priority
GICv3
The GIC uses the group priority field to determine whether a pending interrupt has sufficient priority to preempt
execution on a PE
Virtual FIQ and IRQ are what group?
GICv3
FIQ -> group 0, IRQ -> group1
What controls whether vPE access to ICC_*_EL1 goes to virtual or physical interface?
GICv3
HCR_EL2.{IMO, FMO}
4 Reasons for maintenance interrupts
GICv3
No pending interrupts in the list registers
List registers are (nearly) empty
EOI received for an entry that is not in the list registers
Enabling and disabling of virtual interrupt groups
ICH_VTR_EL2
GICv3
Implementation details
Purpose, One specific use
ICV_CTLR_EL1
GICv3
Control behavior of GIC virtual CPU interface
Virtual EOI Mode
Purpose, two specific uses
ICH_VMCR_EL2
GICv3
Enables the hypervisor to save and restore the virtual machine view of the GIC state
EOI mode, priority mask
what, purpose
ICH_LR<n>_EL2
List registers
Used by hypervisor to present a set of pending virtual interrupts to hardware
Purpose
ICH_EISR_EL2
GICv3
End of interrupt status
ICH_MISR_EL2
GICv3
VM maintenance interrupt status
ICH_AP0R<n>_EL2
GICv3
Active priority status for group 0
