FET

Question 1

How to tell FET drain from source

Answer 1

drain is at positive voltage relative to source by convention

Question 2

What is FET cutoff

Answer 2

Vgs=0, DS is back to back diodes

Question 3

What is enhancement mode FET

Answer 3

normally off, need to control Vgs to turn on

Question 4

What is depletion mode FET

Answer 4

normally on, need to control Vgs to turn off. used as loads in NMOS only process in old CPUs, Motorola 6800 and 6502

Question 5

Describe NMOS

Answer 5

N-type source and drain. P-type substrate. The channel is created by inverting the p-type substrate to n-type with a value of Vgs that is high enough. The channel is also called an inversion layer.

Question 6

How much charge is in the channel

Answer 6

Q=Cox(WL)Vov

Question 7

How to solve for Ids in MOS

Answer 7

(Q/L)(drift velocity)=(Q/m)(m/s)=Q/s=A=(CWVov)(uVds/L) -> Ids = uC*(W/L)(Vov)(Vds) w/o pinch off

Note: Cox = how much charge. un=how fast

Question 8

Regions of MOS operation

Answer 8

Off: Vgs < Vt
Triode: Vds < Vov, Id=f(Vds)
Saturation: Vds > Vov, Id=f(Vov) (pinch-off)

Question 9

How to make PMOS in p-type subtrate?

Answer 9

Need an n-well

Question 10

Best bias for linear NMOS

Answer 10

Saturate so it’s a VCCS with one input.

1) Vgs>Vt,
2) Vds>Vov,
3) Vgd

Question 11

Best bias for linear BJT NPN

Answer 11

NPN in active mode (BC reverse biased)

1) Vbe(on)
2) Vbc < 0.4V
3) Vce > 0.3V

Question 12

what is channel length modulation

Answer 12

As Vdd increases the channel moved away from drain. Since Id is inverse proportional to channel length, as it shortens Id increases with Vds. Lamba is the device parameter. Id=f(Vov)(1+LVds) or (1+Vds/Va)

Question 13

what is the early voltage

Answer 13

specs channel length modulation. output impedance of FET

ro=Va/Id

Question 14

What is the body effect

Answer 14

Changes in Vsb are reflected as a change in Vt

Question 15

How does Vt change with temperature

Answer 15

down by 2mV for every degree C

Question 16

How does Id in FET change with temp?

Answer 16

Vt goes up but Id goes down due to reduced K’

Question 17

What is the level 1 fet Ids equation in linear mode

Answer 17

Id = kn” *(W/L) * (Vov - Vds/2) * Vds

Question 18

What is kn”?

Answer 18

the process transconductance, Un * Cox (Cox=how much) Un=(how fast)

Question 19

How is the small signal requirement derived?

Answer 19

Question 20

When do we prefer the T small signal model?

Answer 20

In general it is preferable whenever there is a resistance connected to the source. Then Rs is in series with that resistance