Electronics 5a - Sequential logic

Question 1

What is the difference between combinational logic and sequential logic?

Answer 1

• Combinational logic gives outputs dependent only on the input at a given time
• Sequential logic circuits do not just depend on inputs at a given time, but may also depend upon previous input states. They are found in memory circuits adn often involve clocks.

Question 2

Draw an S-R flip-flop and state what happends initally and after using the set, reset inputs in the circuit, assuming Q is initailly 1.

Answer 2

S-R flip-flop shown below.

Explaination:
1. Assuming Q is initally 1, and the S and R switches are both 1, then NOT Q will be 0 and the circuit is shown in (i). Note that S and R only active when they are 0 respectively.
2. When R is switched to 0, this changes the NOT Q to go to 1, and the Q to go to 0. shown in (ii)
3. When the R switch returns to 1, the circuit doesn’t change back, shown in (iii).
4. When S is switched to 0, this changes Q to 1 and NOT Q back to 0, shown in (iv).
5. Then S returns to 1, and the circuit is back to its starting condition, shown in (v).

Note:
* S and R are drawn as NOT, as it only activates when 0.
* Also note S and R can’t both be 0 as this would assume that Q and NOT q are equal which isn’t possible.

Question 3

Why can’t the SET and RESET both be at 0 inputs for an S-R flip-flop?

Answer 3

This is because thta would assume Q and NOT Q are both equal to 1, which is not possible by definition.

Question 4

Draw an Clocked S-R flip-flop circuit and mention why it might be used?

Answer 4

Circuit shown below

Note:
* This circuit can only be changed when the clock is high or 1.
* This means there is the potential for better synchronisation.
* Also S and R are now active when logic is 1, instead of 0 like before because of the additional NAND gates.

Question 5

Draw and state the benefit of a level trigger, D-type flip-flop.

Answer 5

Drawn below.

Note:
* Date or D-type flip-flops avoid the issue of S and R both being equal by inverting the input of one signal.
* Now the D input value is copied to the Q output whenever the clock input is at a logic 1 level. This means the flip-flop is said to be ‘Transparent’ where it can only copy the data when the clock is active.
* Level triggered, just referes to it only taking the value of D when the clock is level at high.

Question 6

Draw an edge triggered D-type flip-flop.

Answer 6

Drawn below.

Note:
* There is two flip-flop circuits in this circuit.
* The first one is called the master
* The second one is called the slave
* The D input is passed through the master, outputing the signal to the slave controller
* The D input now at the slave will only go through the slave, once the clock is falling from 1 to 0, due to the inverter, that is why its edge drigger.
* The master requires the clock to be 1, for D input to pass, while the slave requires 0 on the clock, so it triggers the data to pass on the negative edge of the clock.