ECE 368 EXAM 2 Chris Edition

Question 1

What are the 3 concurrent statements?

Answer 1

1) WHEN
2) SELECT
3) GENERATE

Question 2

What are the 4 sequential statements?

Answer 2

1) IF
2) WAIT
3) LOOP
4) CASE

Question 3

What are the 3 kinds a sequential code?

Answer 3

1) PROCESS
2) FUNCTION
3) PROCEDURE

Question 4

(T/F) As a whole, a PROCESS or a subprogram call is a
concurrent statement.

Answer 4

True

Question 5

(T/F) VHDL is inherently sequential.

Answer 5

False

Question 6

Is a process sequential or concurrent

Answer 6

Sequential

Question 7

(T/F) A process is located in the entity section of a VHDL program

Answer 7

False

Question 8

(T/F) A process sensitivity list is mandatory

Answer 8

False

Question 9

(T/F) A variable is optional prior to a process statement

Answer 9

True

Question 10

When is a signal updated in sequential code?

Answer 10

After conclusion of the PROCESS statement

Question 11

Where can VARIABLE be declared and used?

Answer 11

Inside of a PROCESS or subprogram.

Question 12

When are variables updated?

Answer 12

Immediately.

Question 13

(Y/N) are multiple variable assignments allowed?

Answer 13

Yes.

Question 14

How many ways can VHDL pass non-static values? what are they?

Answer 14

Two Ways.
- SIGNAL
- VARIABLE

Question 15

(Y/N) Can signals be global? Can variables be global?

Answer 15

Signals can, but a Variable can NEVER be global.

Question 16

How do you pass the value of a Variable out of a PROCESS?

Answer 16

Assign it to a signal

Question 17

What are the 4 statements for Sequential code?

Answer 17

-IF
-WAIT
-LOOP
-CASE

Question 18

Where can sequential code statements be used?

Answer 18

inside of…
-PROCESS
-FUNCTION
-PROCEDURE

Question 19

What are the pure concurrent statements?

Answer 19

WHEN
SELECT
GENERATE

Question 20

What reserved words indicate that no action should take place?

Answer 20

unaffected
null

Question 21

When can the PROCESS not have a sensitivity list?

Answer 21

When WAIT is Employed

Question 22

What are the three forms of WAIT?

Answer 22

WAIT UNTIL condition; – synthesis
WAIT ON sensitivity_list; – synthesis

WAIT FOR time_expression; – simulation

Question 23

What does WAIT UNTIL do?

Answer 23

This statement causes the process or subprogram
to hold until the expressed condition is fulfilled.

Question 24

Is WAIT UNTIL better for synchronous or asynchronous code?

Answer 24

it is better for synchronous code since it only accepts only one signal.

Question 25

What does WAIT ON do?

Answer 25

This statement causes the process or subprogram to hold
until any listed signal changes.

Question 26

Do WHEN and SELECT have sequential versions?

Answer 26

Yes, VHDL-2008 added these.

Question 27

where is CASE used?

Answer 27

Inside of PROCESS or subprogram

Question 28

what is the main use of CASE?

Answer 28

To enter truth tables into programs.

Question 29

is CASE similar to SELECT?

Answer 29

Yes, All permutations
must be tested, so the keyword OTHERS is often helpful.

Question 30

What is LOOP useful for?

Answer 30

Instantiating the same piece of code multiple times.

Question 31

What is LOOP the counterpart for?

Answer 31

GENERATE.

Question 32

What is GENERATE the counterpart for?

Answer 32

LOOP

Question 33

(T/F) Any circuit with memory is an infinite state
machine

Answer 33

False (FINITE!)

Question 34

What are the two types of state machines?

Answer 34

Mealy and Moore

Question 35

Moore is a function of:

Answer 35

The present state only

Question 36

Mealy is a function of:

Answer 36

The present state and it’s inputs

Question 37

What statement in VHDL best describes FSM?

Answer 37

PROCESS

Question 38

A process used to incorporate an FSM must be sensitive to:

Answer 38

Clock (possibly reset)

Question 39

(T/F) a Mealy machine has less flip-flops than a Moore machine

Answer 39

False (States, only sometimes flip-flops)

Question 40

(T/F) ASM diagrams are similar to FSM’s except they also contain implicit timing information

Answer 40

True

Question 41

What are the three basic elements of an ASM diagram?

Answer 41

1) State box
2) Decision box
3) Conditional output box

Question 42

What is the shape of a state box?

Answer 42

Rectangle

Question 43

What is the shape of a decision box?

Answer 43

Diamond/rhombus

Question 44

What is the shape of a conditional output box?

Answer 44

Oval/ellipse

Question 45

How many states can be active at a time in an ASM?

Answer 45

ONLY ONE!

Question 46

(T/F) Outputs for a mealy machine will be listed inside of a decision box

Answer 46

False (Moore)

Question 47

Where is the name for the state box listed?

Answer 47

Top left corner of the state

Question 48

How many entrance paths does a decision box have? Exit paths?

Answer 48

1, 2

Question 49

(T/F) Outputs for a mealy machine will be listed inside of a conditional output box

Answer 49

True

Question 50

Conditional output boxes are only needed when:

Answer 50

A mealy output is ‘1’.

Question 51

An ASM block consists of:

Answer 51

One state box and the tree of decision
boxes and corresponding conditional output boxes

Question 52

(T/F) Each exit path from an ASM block must connect to a state
box.

Answer 52

True

Question 53

What are the two primary “blocks” used to implement a Datapath?

Answer 53

1) Register file
2) Function unit

Question 54

The two “blocks” that make up the function unit are;

Answer 54

1) ALU
2) Shifter

Question 55

How long is the control word for the Datapath?

Answer 55

16 bits or 2 bytes