ECE 368 Exam 1

Question 1

What is VHDL?

Answer 1

▸VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.
▸Describes the behavior or structure of an electronic circuit or system, from which the physical circuit or system can then be inferred/ implemented by a compiler.

Question 2

Once you have VHDL, you can:

Answer 2

▸Implement the circuit in a programmable device (CPLD/FPGA – complex programmable logic device/field programmable gate array).
▸Layout/mask generation for ASIC (application specific integrated circuit) Fabrication.

Question 3

What does VHDL do?

Answer 3

▸ VHDL is intended for circuit synthesis as well as circuit simulation.
▸ Synthesis: translation of a source code into a hardware structure that implements the intended functionality (converting a higher-level form of a design into a lower-level implementation).
▸ Simulation: a testing procedure to ensure that such functionality is indeed achieved by the synthesized circuit.

Question 4

All statements in VHDL are…

Answer 4

Parallel

Question 5

Optimization

Answer 5

is performed on the gate-level netlist for speed or for area.
▸The design can be simulated at this stage.

Question 6

Place & Route

Answer 6

will generate the physical layout for
an FPGA chip or will generate the
masks for an ASIC.

Question 7

Entity

Answer 7

Specifies the I/O ports of the circuit, plus (optional) generic constants.

Question 8

Architecture

Answer 8

Contains the VHDL code proper, which describes how the circuit behaves, from which a compliant hardware is inferred.

Question 9

Rules to name Identifiers (names that can be given by the user)?

Answer 9

▸ Must start with an alphabetic letter.
▸ Can contain alphabetic letters, decimal digits and underline character “”.
▸ Cannot end with “”.
▸ Cannot contain successive “__”.

Question 10

Library Declarations

Answer 10

lists all libraries and respective packages needed in the design (the most commonly used libraries are IEEE, STD, WORK. STD and WORK are made visible by default).

Question 11

Three fundamental sections that
comprise a piece of VHDL code:

Answer 11

Entity, Architecture, Library Declarations

Question 12

Library

Answer 12

is a collection of
commonly used pieces of code.
Placing them inside a library
allows the code to be reused and
shared by other designs.

Question 13

Within VHDL we can describe
the logic in three different
manners. These three different
architectures are:

Answer 13

‣ Dataflow
‣ Structural
‣ Behavioral
‣ Concurrent
‣ Sequential

Question 14

Data Flow Style

Answer 14

Describes how the data flows from the
inputs to the output most often using NOT,
AND and OR operations.

Question 15

Structural VHDL allows the designer to represent…

Answer 15

a system in terms of components and their interconnections.

Question 16

Basic structural modeling includes:

Answer 16

‣ Design ENTITY modeled as a set of interconnected components.
‣ Components are
‣ Declared using component declaration.
‣ Instantiated using component instantiation statements.
‣ Interconnected using signals.

Question 17

Component Declaration

Answer 17

Defines kind of module used, specifies external interface to component in terms of generic constants and ports.

Question 18

Component declaration uses:

Answer 18

‣ The same name of component as entity of the component module.
‣ The same port declaration as module entity declared as component.

Question 19

Component Instantiation

Answer 19

‣ Specifies usage of module in design.
‣ Inside architecture body (after BEGIN).
‣ Note, components can be described either structurally or behaviorally in separate entities treating these components as independent designs (subsystems).

Question 20

Port Position - By Name

Answer 20

‣ Order of listed component ports in port map irrelevant.
‣ Need to specify explicitly names of component port and its corresponding design port.
‣ Assignment by “=>”, left would be the declared component port name, right would be the entity port name or the signal.

Question 21

Port Position - By Position

Answer 21

‣ Order of component ports in port map important.
‣ Explicitly assumed to be the same as in component declaration – no need to mention component names!
‣ Order is important!

Question 22

VHDL Objects

Answer 22

• An object is a named item of a specific type that has a value of a type.
• Objects constitute the means through which values are passed around.
• Such VHDL objects are CONSTANT, SIGNAL, VARIABLE, and FILE.

Question 23

CONSTANT

Answer 23

▸ An object whose value cannot be changed.

▸ Simplified syntax for the declaration of constants is: CONSTANT constant_name: constant_type := constant_value;
▸ Name can be essentially any word, except reserved words.
▸ Type can be any VHDL type
▸ Value can be a constant or an expression involving constants.
▸ Make the code more readable; avoid using numeric values; and prevent errors when the value of a constant must be modified.

Question 24

Deferred CONSTANT:

Answer 24

a constant declared without its value is said to be a deferred constant. Such a declaration
is allowed in a PACKAGE, but then the complete specification including the value must appear in the corresponding PACKAGE BODY.

Question 25

Keyword OTHERS:

Answer 25

it is a useful keyword for making assignments. It represents all index value thatwere left unspecified.

Question 26

SIGNAL

Answer 26

▸ Passes values in and out of the circuit, as well as between its internal units.
▸ A signal represents circuit interconnects (wires)
▸ All ports of an entity are signals by default.
▸ Signal declarations can be made in the declarative part.
▸ Signal declarations are not allowed in sequential code (i.e., PROCESS and subprograms), but signals can be used
there (its update is not immediate).
▸ A simplified syntax for signal declarations is:
SIGNAL signal_name: signal_type[range] [:= default_value];

▸ If default value is optional; if not included, an implicit value is assumed, which is the type’s leftmost value
▸ For integers, it is the range’s left bound
▸ For enumeration types, it is the first element in the list

Question 27

VARIABLE

Answer 27

▸ VARIABLE represents only local information
▸ It can only be seen and modified inside the sequential unit
(i.e., PROCESS or subprogram) where it was created.
▸ Its update is immediate, so the new value can be promptly used in the next line of code. And multiple assignments to the same variable are fine.
▸ A simplified syntax for variable declarations is: VARIABLE variable_name: variable_type[range] [:= default_value];

Question 28

FILE

Answer 28

▸ Not for synthesis but for simulation.
▸ File declarations make a file available for use to a design.
▸ To declare an object of FILE, a FILE type must first be created.

Question 29

FILE TYPE

Answer 29

▸ FILE type: contains the name chosen to represent the type and the type of the data contained in the file (only one type is allowed).
TYPE type_name IS FILE OF type_in_file

Question 30

FILE OBJECT

Answer 30

▸ FILE object: contains an identifier chosen to represent that object, followed by the type name, then the optional keyword OPEN with
the corresponding file-open mode (read_mode, write_mode, or append_mode, defined in the package standard of the library std). The expression at the end is a file name between double quotes.
FILE file_identifier: type_name [[OPEN open_mode] IS expression];

Question 31

Predefined data type

Answer 31

defined in the provided VHDL packages

Question 32

User-defined data type

Answer 32

defined by the user to handle specific situations.

Question 33

▸A scalar type is declared using…

Answer 33

the keyword type.

Question 34

▸An array type is declared using…

Answer 34

the keyword type and array.

Question 35

SUBTYPE

Answer 35

A subtype is a type with some constraint.

Question 36

BIT

Answer 36

▸ 2-value enumerated type: ‘0’, ‘1’
▸ It supports logical and comparison operations.
TYPE BIT IS (‘0’, ‘1’)

Question 37

BIT_VECTOR

Answer 37

▸ The vector form of BIT (1D array)
▸ It supports logical, comparison, shift, and concatenation operations.
TYPE BIT_VECTOR IS ARRAY (NATURAL RANGE <>) OF BIT;
Natural range default=0 to 2^31 − 1
▸ For logical and shift operations, the vectors are required to have the same length.

Question 38

BOOLEAN

Answer 38

▸ Another 2-value enumerated type: FALSE, TRUE
▸ It supports logical and comparison operations.
TYPE BOOLEAN IS (FALSE, TRUE)

Question 39

BOOLEAN VECTOR

Answer 39

▸ The vector form of BOOLEAN (1D array)
▸ It supports logical, comparison, shift, and concatenation operations.
TYPE BOOLEAN_VECTOR IS ARRAY (NATURAL RANGE <>) OF BOOLEAN;

Question 40

INTEGER

Answer 40

▸ Default range of INTEGER consists of a 32-bit representation from −(2!”) to +(2!” − 1). The actual bounds are referred to as INTEGER’LOW (on the left) and INTEGER’HIGH (on the right).
▸ It supports arithmetic and comparison operations.
TYPE INTEGER IS RANGE implementation_defined;
TYPE INTEGER IS RANGE -2147483648 TO 2147483647;
▸ For synthesis, it is important to always specify the range for objects of type INTEGER, otherwise, the compiler will employ 32-bit to represent them.

Question 41

NATURAL

Answer 41

▸ Non-negative integers. It is a subtype of INTEGER.
SUBTYPE NATURAL IS INTEGER RANGE 0 TO INTEGER’HIGH;

Question 42

POSITIVE

Answer 42

Positive integers. It is a subtype of INTEGER.
SUBTYPE POSITIVE IS INTEGER RANGE 1 TO INTEGER’HIGH;

Question 43

INTEGER_VECTOR

Answer 43

▸ The vector form of INTEGER (1D x 1D array).
▸ Supports comparison and concatenation operations.
TYPE INTEGER_VECTOR IS ARRAY (NATURAL RANGE <>) OF INTEGER;
Natural range <> informs that the range is
unconstrained with the only limitation that it must fall within the natural range (0 to 2^31-1)

Question 44

CHARACTER

Answer 44

▸ A 256-symbol enumerated type.
▸ Supports only comparison operations.
TYPE CHARACTER IS (NUL, SOH, …, ‘0’, ‘1’, ‘2’, …);
▸ The symbols are from the ISO 8859-1 character set, with the first 128 symbols comprising the regular ASCII code.
▸ Each symbol is represented by 8-bit (1D array).
▸ A single character is written in single quotes.

Question 45

STRING

Answer 45

▸ The vector form of CHARACTER (1D x 1D array).
▸ Supports comparison and concatenation operations.
TYPE STRING IS ARRAY (POSITIVE RANGE <>) OF CHARACTER;

Question 46

STD_ULOGIC

Answer 46

is unresolved

Question 47

STD_LOGIC

Answer 47

resolved.

Question 48

TRI-STATE BUFFER

Answer 48

▸ To artificially create some delay.
▸ To increase current that a gate is feeding to other devices.

Question 49

BUFFER

Answer 49

▸ The AND gate has a fanout of 4.
▸ If each of the four devices gets equal current, then each device gets ¼ of the initial current.
▸ Adding a buffer can boost current
to each device.

Question 50

What is High Impedance (Z)?

Answer 50

▸ In electronics, high impedance means that a point in a circuit (a node) allows a relatively small amount of current through. High impedance circuits are low current, high
voltage.
▸ In digital electronics, a high impedance output is not being driven to any defined logic level by the output circuit. The signal is neither driven to a logical high nor logical low. The third condition leads to the description “tri-stated”.
▸ Open circuit or “floating” wire.
▸ This is the basis for bus-systems in computers.

Question 51

Why Tri-State Buffer?

Answer 51

▸ A common way for many devices to communicate with one another is on a bus.
▸ A bus should only have one device writing to it, although it can have many devices reading from it.
▸ Since many devices always produce output, such as registers, and these devices are hooked to a bus, we need a way to control what gets on the bus, and what doesn’t.

Question 52

STD_ULOGIC/STD_ULOGIC_VECTOR

Answer 52

▸ 9-valued logic system introduced in IEEE 1164 standard.
▸ ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’, ‘U’ – unresolved
▸ STD_LOGIC is a subtype of STD_ULOGIC,and
STD_LOGIC_VECTOR is a subtype of STD_ULOGIC_VECTOR.
▸ Conflicting logic levels are not automatically resolved here
=> output wires should never be connected together directly.

Question 53

PREDEFINED UNSIGNED DATA TYPE

Answer 53

▸ Must declare numeric_std package in the code.
▸ The base type is STD_ULOGIC.
TYPE UNRESOLVED_UNSIGNED IS ARRAY (NATURAL RANGE <>) OF STD_ULOGIC;
SUBTYPE UNSIGNED IS (RESOLVED) UNRESOLVED_UNSIGNED;
▸ The subtype is a resolved version of the type above.
▸ It is recommended alternative for implementing unsigned integer arithmetic circuits.

Question 54

PREDEFINED SIGNED DATA TYPE

Answer 54

▸ Must declare numeric_std package in the code.
▸ The base type is STD_ULOGIC.
TYPE UNRESOLVED_SIGNED IS ARRAY (NATURAL RANGE <>) OF STD_ULOGIC;
SUBTYPE SIGNED IS (RESOLVED) UNRESOLVED_SIGNED;
▸ The subtype is a resolved version of the type above.
▸ It is recommended alternative for implementing signed integer
arithmetic circuits.

Question 55

FIXED-POINT TYPES

Answer 55

▸ Fixed-point types and subtypes are defined in the package fixed_generic_pkg.
▸ They are intended for arithmetic circuits, only logic values ‘0’ and ‘1’ should be used.
▸ Range must always be descending from L down to R, where L (left) is usually positive and R (right) is usually negative.
▸ The integer part is formed by non-negative indexes, while the fraction is formed by the negative indexes.

Question 56

FLOATING-POINT TYPES

Answer 56

▸ Floating-point types and subtypes are defined in the package float_generic_pkg.
▸ They are intended for arithmetic circuits, only logic values ‘0’ and ‘1’ should be used.
▸ The range must always be descending, from L down to R. The leftmost bit (S) is the sign bit, the next Ewidth bits form the exponent (E), and the final Fwidth bits form the fraction
(F). Note that Ewidth = L and Fwidth =−R.

Question 57

REAL

Answer 57

▸ Not intended for synthesis.
▸ Has some synthesis support for static values, so it can be helpful for defining general circuit parameters.
▸ Available in math_real package.

Question 58

DATA AGGREGATION

Answer 58

▸ To build an aggregate, we write the elements to be combined within parentheses, separated by commas.
▸ The keyword others, when used, must come last.
▸ Aggregate single elements of the base type or arrays of the base type.

Question 59

DATA CONCATENATION

Answer 59

▸ Concatenation operator (&) can join individual elements of the base type as well as arrays of the base type.
▸ Use of parentheses is optional.
▸ Keyword others is not allowed.
▸ Concatenation of aggregates is legal.

Question 60

DATA ARRAY RESIZING

Answer 60

▸ The resize function can be used to extend or reduce the size of arrays.
▸ The function is available in several packages, for several data types.

Question 61

DATA TYPE CONVERSION – AUTOMATIC CONVERSION

Answer 61

▸ Occurs when dealing directly with the base type.
▸ Bit and bit_vector have the same base type bit.
▸ std_(u)logic_vector, unsigned, signed, ufixed, sfixed, and float have std_ulogic as base type.

Question 62

DATA TYPE CONVERSION – CAST

Answer 62

▸ To perform the conversion, we write the name of the target type, followed by the object to be converted between parentheses.
▸ A very common use of type cast is in arithmetic circuits.
▸ The standard-logic types be used for circuit ports whenever possible, but if the circuit does arithmetic with integers, such signals should be converted internally to unsigned or signed and back to standard-logic types after the computations to be sent out.

Question 63

DATA TYPE CONVERSION – FUNCTIONS

Answer 63

▸ A specific type-conversion function:
to_target_type(argument [, specifications]);
▸ Table 7.10.
▸ The argument field consists of an object of one of the types or subtypes listed in the first column of Table 7.10.

Question 64

Within VHDL we can describe the logic in three different manners. These three different architectures are:

Answer 64

‣ Structural
‣ Dataflow
‣ Behavioral

Question 65

DATA FLOW STYLE

Answer 65

• Describes how the data flows from the inputs to the output most often using NOT, AND and OR operations.

Question 66

BEHAVIORAL STYLE

Answer 66

• Describes how the output is derived from the inputs using structured statements.
  ‣ Concurrent Statements
  ‣ Sequential Statements

Question 67

Concurrent Code

Answer 67

‣ is intended only for the design of combinational circuits.
‣ A process body or a subprogram call is also a concurrent statement.

Question 68

Sequential Code

Answer 68

‣ can be used to design both sequential and combinational circuits.
‣ Only statements places inside a PROCESS, FUNCTION, or PROCEDURE are executed sequentially

Question 69

Concurrent Logic:

Answer 69

‣ Output depends only on the current inputs;
‣ No memory, and can be implemented using
conventional logic gates.
‣Concurrent statements are order independent and asynchronous
‣ Concurrent code is also called data flow code.

Question 70

Sequential Logic:

Answer 70

‣ Output depends on the inputs and the history of the input;
‣ Storage elements are required to store the states created by previous inputs. They are connected to the combinational logic block through a feedback loop.

Question 71

Concurrent Statements

Answer 71

‣ are order-independent and asynchronous.
‣ Concurrent code is also called data flow code.
Three purely concurrent statements:
‣ WHEN, SELECT, and GENERATE
All statements execute at the same time (logic circuits).

Question 72

Sequential Statements

Answer 72

‣ view hardware from a “programmer” approach.
Four purely sequential statements:
‣ IF, WAIT, LOOP, and CASE
Statements execute in series (programming languages as C).

Question 73

WHEN

Answer 73

‣ WHEN is one of the fundamental concurrent statement.
‣ It is approximately equivalent to the sequential statement IF.
‣ A simplified syntax for WHEN:
assignment_expression WHEN conditions ELSE assignment_value WHEN conditions ELSE
……;

Question 74

UNAFFECTED

Answer 74

should be used when no action is to take place. Use it only when memorization of the previous system state is indeed wanted.

Question 75

SELECT

Answer 75

‣ SELECT is another concurrent statement.
‣ It is approximately equivalent to the sequential statement CASE.
‣ A simplified syntax for SELECT:
WITH identifier SELECT
assignment_expression WHEN values,
assignment_value WHEN values,
……;

Question 76

GENERATE

Answer 76

‣ GENERATE is another concurrent statement.
‣ It is approximately equivalent to the sequential statement LOOP. It has a section of code repeated a number of times.
‣ Unconditional GENERATE
‣ Conditional GENERATE

Question 77

GENERATE STATEMENT – UNCONDITIONAL GENERATE

Answer 77

‣ FOR-GENERATE
‣ Used to create multiple instances of a section of code.
‣ A simplified syntax :
label: FOR identifier IN range GENERATE
[declarative_part
BEGIN];
concurrent_statement_part;
END GENERATE;
A label is required.
BEGIN is only needed when
declarations are made.

Question 78

GENERATE STATEMENT – CONDITIONAL GENERATE

Answer 78

‣ IF-GENERATE
‣ Includes an IF statement in the GENERATE loop.
‣ A simplified syntax :
label: IF condition GENERATE
concurrent_statements;
[ELSIF condition GENERATE
concurrent_statements;]
[ELSE GENERATE
concurrent_statements;]
END GENERATE [label];

‣ CASE-GENERATE
‣ Includes a CASE statement in the GENERATE loop.
‣ A simplified syntax :
label: CASE expression GENERATE
WHEN choice =>
concurrent_statements;
WHEN choice =>
concurrent_statements;
…
END GENERATE [label];

Question 79

STATIC RANGE

Answer 79

‣ Range limit is normally required to be static.
‣ If x is an input, then it’s a non-static parameter. The code
might not be synthesizable.

Question 80

GENERIC

Answer 80

‣ A GENERIC is VHDL’s term for a parameter that passes information to an entity.
‣ Generics allow a design entity to be described so that, for each use of that component, its structure and behavior can be changed by generic values.
‣ In general they are used to construct parameterized hardware components.
Generics can be of any type.
‣ Generic parameters are ”connected” to values using a GENERIC MAP that functions just as a PORT MAP does for signals.

‣ GENERIC declaration section is in ENTITY before PORT.
ENTITY entity_name IS
GENERIC (const_name: const_type:=const_value; …);
PORT (signal_name: mode signal_type; …);
END entity_name;
‣ GENERIC is the only declaration allowed before the PORT.
‣ Such constants are truly global because they can be used even in the PORT specifications.
GENERIC (const_name: const_type:= const_value; …);

Question 81

GENERIC MAP

Answer 81

may exist in a component instantiation, in a configuration declaration or in a BLOCK instantiation. The generic parameters may also be assigned values in the simulator or in the synthesis tool.

‣ If a COMPONENT containing a GENERIC declaration is instantiated in another design, the values of the generic constants that appear in the component being instantiated
can be overwritten by the main design.

Question 82

GENERIC MAP: COMPONENT DECLARATION

Answer 82

‣ The COMPONENT declaration is an exact copy of the ENTITY of the design being instantiated.
‣ The GENERIC specification only needs to be included if the component contains a GENERIC list and one or more values in that list must be changed by the instantiating design.

COMPONENT component_name IS
GENERIC (const_name: const_type := const_value; const_name: const_type := const_value;
……..);
PORT ( port_name: port_mode signal_type;
port_name: port_mode signal_type;
……..);
END COMPONENT;

Question 83

GENERIC MAP: COMPONENT INSTANTIATION

Answer 83

‣ GENERIC MAP is necessary when the original component has a GENERIC specification in the ENTITY header and one or more of its values must be overwritten by the new design.
Label: [COMPONENT] component_name
[GENERIC MAP (generic_list)] PORT MAP (port_list);

Question 84

GENERIC PROPERTIES

Answer 84

‣ Generics are constant.
‣ The values of generics must be known at compile time.
‣ They are a part of the interface specification but do not have a physical interpretation.
‣ Use of generics is not limited to “delay like” parameters and are in fact a very powerful structuring mechanism.

‣ “GENERIC” is a great asset when you use your design at many places with slight change in the register sizes, input sizes etc. But if the design is very unique then, you need not have generic parameters.
‣ Generic is synthesizable.