ECE 368 EXAM 1 Chris Edition Flashcards
How do you convert a binary number to two’s compliment (assuming a negative value is desired)?
Change all 0’s to 1’s and all 1’s to 0’s, then add 1 to the final result
How do you convert a binary number to a hexadecimal number?
Take groups of four bits starting from the right of the binary number and transform them to the corresponding.
How do you convert a binary number to one’s compliment (assuming a negative value is desired)?
Change all 0’s to 1’s and all 1’s to 0’s
What does VHDL stand for?
VHSIC (Very High Speed Integrated Circuit) Hardware
Description Language
What is the main purpose for using VHDL?
Circuit synthesis and implementation with an FPGA
What is synthesis in VHDL?
The translation of source code into a hardware
structure that implements the intended functionality
What is simulation in VHDL
A testing procedure to ensure that such
functionality is indeed achieved by the synthesized circuit
Are all constructs in VHDL able to be simulated?
Yes
Are all constructs in VHDL able to be synthesized?
No
Are statements in VHDL (With exception of process) executed in parallel or series?
Parallel
Is VHDL case sensitive?
No (With a single exception)
How do you trigger comments in VHDL?
By using a ‘- -‘ (Double dash)
How do you terminate a statement in VHDL?
By using a ‘;’
Identifiers in VHDL must always start with:
An alphabetic letter
Identifiers in VHDL can contain:
Letters, digits, and the ‘_’ character
Can a VHDL identifier end with ‘_’?
No
Can a VHDL identifier contain successive ‘_’ characters (ex: ‘__’) ?
No
Are the following identifiers valid?
1) A
2) X0
3) last@value
4) Next_Value
5) 5bit_counter
6) _A0
7 ) A0_
8) Clock__Pulse
1) Yes
2) Yes
3) No (Can’t have ‘@’)
4) Yes
5) No (Can’t start with ‘5’)
6) No (Can’t start with ‘_’)
7) No (Can’t end with ‘_’)
8) No (Can’t contain '__’)
What are the 3 fundamental VHDL code sections?
1) Library Declarations
2) Entity
3) Architecture
What does the Library Declarations section of VHDL code consist of?
Lists all libraries and respective packages needed in the design
What does the Entity section of VHDL code consist of?
Specifies the I/O ports of the circuit, plus (optional) generic constants
What does the Architecture section of VHDL code consist of?
Describes how the circuit behaves, from which a compliant hardware is inferred.
What are the three different VHDL architectures?
1) Structural
2) Behavioral
3) Dataflow
How does the dataflow architecture work?
Describes how the data flows from the inputs to the output most often using NOT, AND and OR operations.
Structural VHDL allows the designer to represent a system in terms of ______________ and their ______________.
1) Components
2) Interconnections
(T/F) Structural descriptions can show a more concrete relation between code and physical hardware.
True
(T/F) Behavioral descriptions show interconnections at any level of abstraction.
False (This would be true if Behavioral were replaced by Structural)
In structural architecture, how are components interconnected?
With the use of signals
In structural architecture, how are components declared? (Obvious answer)
With component declarations
In structural architecture, how are components instantiated? (OBVIOUS ASS ANSWER)
With component instantiation statements
What is component declaration in structural VHDL?
Defines kind of module used, specifies external interface
to component in terms of generic constants and ports.
(T/F) A different name for the component in comparison to the entity of the component module is used for component declaration
False (The same name is used)
(T/F) Component declaration uses the same port declaration as a module entity declared as component
True
(T/F) Component declaration is outside architecture body with signal declaration
False (Inside the architecture body, just before the ‘BEGIN’)
(T/F) Component instantiation is located outside architecture body
False (Inside the architecture body, just after the ‘BEGIN’)
What is component instantiation?
Specifies usage of module in design
What are the two ways ports can be assigned?
1) By name
2) By position
(T/F) Order is not important when assigning ports by position
False (Position is crucial)
How do you assign ports by name in VHDL (Syntax)?
Name_of_component_port => Entity_Port_name_or_signal
(T/F) The order of component ports is explicitly assumed to be the same as in component declaration
True
Are \clk\, \CLK\, and \Clk\ considered different names/identifiers?
Yes (VHDL is not case sensitive only when identifier surrounded by backslashes)
Is arch a reserved VHDL word?
No
What is an identifier used for in VHDL?
They are used to name VHDL items such as signals, variables, entity declarations, etc.
What delimiter is used to assign a value to a signal?
<=
What delimiter is used to assign a value to a variable, constant, and initial value of a signal?
:=
How many bits does the type integer operate with?
Up to 32 bits
(T/F) Xnor is a reserved VHDL word
True
(T/F) a delimiter with one character is referred to as a compound delimiter.
False (This is a simple delimiter)
How many synthesizable characters are there in VHDL?
256
(T/F) Single quotes indicate a single character/bit whereas double quotes indicate a string of characters/bits
True
(T/F) Component is a VHDL reserved word
True
(T/F) The “.all” extension makes all elements of a certain package visible
True
What is an object in VHDL?
An object is a named item of a specific type that has a
value of said type.
What are the four VHDL objects?
1) Signal
2) Variable
3) Constant
4) File
(T/F) Objects declared in a process are available to all VHDL descriptions
False (Only available to within process)
(T/F) Objects declared in an entity are available to all
architectures associated with that entity
True
(T/F) Objects declared in an architecture are available to all statements in the entity
False (Only available within the scope of the architecture)
(T/F) Objects declared in an entity are available to all
architectures associated with that entity as well as the architecture
False (Only available within the scope of the entity)
What is a constant in VHDL?
An object whose value can not be changed
Syntax: CONSTANT constant_name: constant_type := constant_value;
What VHDL type can a constant be?
Any!!!
What is a deferred constant?
A constant declared without its value
What does the keyword others help to accomplish?
Represents all index value that were left unspecified
Syntax Example: CONSTANT b: BIT_VECTOR(7 DOWNTO 0) := (7 => ‘0’, OTHERS => ‘1’)
What is a signal in VHDL?
An object that passes values in and out of the circuit, as well as between its internal units (i.e a wire).
Syntax: SIGNAL signal_name: signal_type[range] [:= default_value];
Are signal declarations allowed in sequential code?
FOOO
Can signals be used in sequential code?
Yes
(T/F) All ports of an entity are constants by default
False (Signals)
(T/F) Default values for signals is recommended in code that is for synthesis
False (Not recommended in synthesis code)
What is a variable in VHDL?
An object that represents local information
Syntax: VARIABLE variable_name: variable_type[range] [:= default_value];
Name the 10 synthesizable data types from standard package
1) BIT
2) BIT_VECTOR
3) BOOLEAN
4) BOOLEAN_VECTOR
5) INTEGER
6) NATURAL
7) POSITIVE
8) INTEGER_VECTOR
9) CHARACTER
10) STRING
(T/F) A scalar type is declared using the keyword type.
True
Syntax: type type_name is type_definition
(T/F) An array type is declared using the keyword type and vector.
False (vector should be array)
Syntax: type type_name is array (range_spec) of base_type_name [range_spec]
