ECE 368 EXAM 1 Chris Edition Flashcards
How do you convert a binary number to two’s compliment (assuming a negative value is desired)?
Change all 0’s to 1’s and all 1’s to 0’s, then add 1 to the final result
How do you convert a binary number to a hexadecimal number?
Take groups of four bits starting from the right of the binary number and transform them to the corresponding.
How do you convert a binary number to one’s compliment (assuming a negative value is desired)?
Change all 0’s to 1’s and all 1’s to 0’s
What does VHDL stand for?
VHSIC (Very High Speed Integrated Circuit) Hardware
Description Language
What is the main purpose for using VHDL?
Circuit synthesis and implementation with an FPGA
What is synthesis in VHDL?
The translation of source code into a hardware
structure that implements the intended functionality
What is simulation in VHDL
A testing procedure to ensure that such
functionality is indeed achieved by the synthesized circuit
Are all constructs in VHDL able to be simulated?
Yes
Are all constructs in VHDL able to be synthesized?
No
Are statements in VHDL (With exception of process) executed in parallel or series?
Parallel
Is VHDL case sensitive?
No (With a single exception)
How do you trigger comments in VHDL?
By using a ‘- -‘ (Double dash)
How do you terminate a statement in VHDL?
By using a ‘;’
Identifiers in VHDL must always start with:
An alphabetic letter
Identifiers in VHDL can contain:
Letters, digits, and the ‘_’ character
Can a VHDL identifier end with ‘_’?
No
Can a VHDL identifier contain successive ‘_’ characters (ex: ‘__’) ?
No
Are the following identifiers valid?
1) A
2) X0
3) last@value
4) Next_Value
5) 5bit_counter
6) _A0
7 ) A0_
8) Clock__Pulse
1) Yes
2) Yes
3) No (Can’t have ‘@’)
4) Yes
5) No (Can’t start with ‘5’)
6) No (Can’t start with ‘_’)
7) No (Can’t end with ‘_’)
8) No (Can’t contain '__’)
What are the 3 fundamental VHDL code sections?
1) Library Declarations
2) Entity
3) Architecture
What does the Library Declarations section of VHDL code consist of?
Lists all libraries and respective packages needed in the design
What does the Entity section of VHDL code consist of?
Specifies the I/O ports of the circuit, plus (optional) generic constants
What does the Architecture section of VHDL code consist of?
Describes how the circuit behaves, from which a compliant hardware is inferred.
What are the three different VHDL architectures?
1) Structural
2) Behavioral
3) Dataflow
How does the dataflow architecture work?
Describes how the data flows from the inputs to the output most often using NOT, AND and OR operations.
Structural VHDL allows the designer to represent a system in terms of ______________ and their ______________.
1) Components
2) Interconnections
(T/F) Structural descriptions can show a more concrete relation between code and physical hardware.
True
(T/F) Behavioral descriptions show interconnections at any level of abstraction.
False (This would be true if Behavioral were replaced by Structural)
In structural architecture, how are components interconnected?
With the use of signals
In structural architecture, how are components declared? (Obvious answer)
With component declarations
In structural architecture, how are components instantiated? (OBVIOUS ASS ANSWER)
With component instantiation statements
What is component declaration in structural VHDL?
Defines kind of module used, specifies external interface
to component in terms of generic constants and ports.
(T/F) A different name for the component in comparison to the entity of the component module is used for component declaration
False (The same name is used)
(T/F) Component declaration uses the same port declaration as a module entity declared as component
True
(T/F) Component declaration is outside architecture body with signal declaration
False (Inside the architecture body, just before the ‘BEGIN’)
(T/F) Component instantiation is located outside architecture body
False (Inside the architecture body, just after the ‘BEGIN’)
What is component instantiation?
Specifies usage of module in design
What are the two ways ports can be assigned?
1) By name
2) By position
(T/F) Order is not important when assigning ports by position
False (Position is crucial)
How do you assign ports by name in VHDL (Syntax)?
Name_of_component_port => Entity_Port_name_or_signal
(T/F) The order of component ports is explicitly assumed to be the same as in component declaration
True
Are \clk\, \CLK\, and \Clk\ considered different names/identifiers?
Yes (VHDL is not case sensitive only when identifier surrounded by backslashes)
Is arch a reserved VHDL word?
No
What is an identifier used for in VHDL?
They are used to name VHDL items such as signals, variables, entity declarations, etc.
What delimiter is used to assign a value to a signal?
<=
What delimiter is used to assign a value to a variable, constant, and initial value of a signal?
:=
How many bits does the type integer operate with?
Up to 32 bits
(T/F) Xnor is a reserved VHDL word
True
(T/F) a delimiter with one character is referred to as a compound delimiter.
False (This is a simple delimiter)
How many synthesizable characters are there in VHDL?
256
(T/F) Single quotes indicate a single character/bit whereas double quotes indicate a string of characters/bits
True
(T/F) Component is a VHDL reserved word
True
(T/F) The “.all” extension makes all elements of a certain package visible
True
What is an object in VHDL?
An object is a named item of a specific type that has a
value of said type.
What are the four VHDL objects?
1) Signal
2) Variable
3) Constant
4) File
(T/F) Objects declared in a process are available to all VHDL descriptions
False (Only available to within process)
(T/F) Objects declared in an entity are available to all
architectures associated with that entity
True
(T/F) Objects declared in an architecture are available to all statements in the entity
False (Only available within the scope of the architecture)
(T/F) Objects declared in an entity are available to all
architectures associated with that entity as well as the architecture
False (Only available within the scope of the entity)
What is a constant in VHDL?
An object whose value can not be changed
Syntax: CONSTANT constant_name: constant_type := constant_value;
What VHDL type can a constant be?
Any!!!
What is a deferred constant?
A constant declared without its value
What does the keyword others help to accomplish?
Represents all index value that were left unspecified
Syntax Example: CONSTANT b: BIT_VECTOR(7 DOWNTO 0) := (7 => ‘0’, OTHERS => ‘1’)
What is a signal in VHDL?
An object that passes values in and out of the circuit, as well as between its internal units (i.e a wire).
Syntax: SIGNAL signal_name: signal_type[range] [:= default_value];
Are signal declarations allowed in sequential code?
FOOO
Can signals be used in sequential code?
Yes
(T/F) All ports of an entity are constants by default
False (Signals)
(T/F) Default values for signals is recommended in code that is for synthesis
False (Not recommended in synthesis code)
What is a variable in VHDL?
An object that represents local information
Syntax: VARIABLE variable_name: variable_type[range] [:= default_value];
Name the 10 synthesizable data types from standard package
1) BIT
2) BIT_VECTOR
3) BOOLEAN
4) BOOLEAN_VECTOR
5) INTEGER
6) NATURAL
7) POSITIVE
8) INTEGER_VECTOR
9) CHARACTER
10) STRING
(T/F) A scalar type is declared using the keyword type.
True
Syntax: type type_name is type_definition
(T/F) An array type is declared using the keyword type and vector.
False (vector should be array)
Syntax: type type_name is array (range_spec) of base_type_name [range_spec]
What is a subtype in VHDL?
A subtype is a type with a constraint
(T/F) Type Bit can either be TRUE or FALSE
False (Either ‘1’ or ‘0’)
(T/F) Type Bit supports logic operations (OR, AND, etc.)
True
What is a bit vector in VHDL (Yes its as obvious as you think)
A vector of bits (Told you)
What four operations does a bit vector support?
1) Logical
2) Comparison
3) Shift
4) Concatenation
(T/F) For logical and shift operations, the vectors are required to have half the length of the output signal.
False (Lengths must be the same)
What two values can type Boolean be?
True and False
(T/F) The Boolean vector supports the same four operations as a bit vector (Logical, Comparison, Shift, and Concatenation)
True
(T/F) The actual bounds are referred to as INTEGER’LOW (on the left) and INTEGER’HIGH (on the right)
True
(T/F) Natural is a subtype of Boolean
False (It is a subtype of integer)
(T/F) Natural is a subtype of bit
False (It is a subtype of integer)
What two operations does the integer type support?
1) Arithmetic
2) Comparison
What operator does type character support?
Comparison
How many bits are required to represent a character?
8 bits (1 byte)
(T/F) A string is an array type of character
True
What are the nine values type std_logic can take on?
1) ‘X’ (Forced unknown)
2) ‘0’ (Forced low)
3) ‘1’ (Forced High)
4) ‘Z’ (High Impedance)
5) ‘W’ (Weak unknown)
6) ‘L’ (Weak low)
7) ‘H’ (Weak high)
8) ‘/-‘ (Don’t care)
9) ‘U’ (Unresolved)
What are three benefits of using a tri-state buffer?
1) Artificially create delay
2) Increase current fed to other devices
3) Controls what devices are able to access a data bus
(T/F) High impedance circuits are high current, low voltage (A wire)
False (High voltage, low current (An open))
What is the output for a Tri-state buffer when the control is low? What is the output for a Tri-state buffer when the control is high?
1) High impedance (Z)
2) The value seen at the input
(T/F) STD_ULOGIC is a subtype of STD_LOGIC
False (STD_LOGIC is a subtype of STD_ULOGIC)
(T/F) STD_LOGIC_VECTOR is a subtype of STD_ULOGIC_VECTOR
FALSE (BACKWARDS)
What are the types signed and unsigned subtypes of?
std_logic
What are the types fixed and float subtypes of?
std_logic
LEGAL OR ILLEGAL
SIGNAL a: BIT;
SIGNAL b: BIT_VECTOR (7 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL e: INTEGER RANGE 0 TO 255;
1) a <= b(5);
2) b(0) <= a;
3) c <= d(5);
4) d(0) <= c;
5) a <= c;
6) b <= d;
7) e <= b;
8) e <= d;
1) LEGAL
2) LEGAL
3) LEGAL
4) LEGAL
5) ILLEGAL (TYPE MISMATCH)
6) ILLEGAL (TYPE MISMATCH)
7) ILLEGAL (TYPE MISMATCH)
8) ILLEGAL (TYPE MISMATCH)
What is the identifier used for data concatenation?
&
(T/F) When aggregating data, the others keyword must come first
False (Must come last)
EX: (‘1’, ‘1’, others => ‘0’)
(T/F) Concatenation of aggregates is legal
True
(T/F) Parenthesis are mandatory for concatenation
False (Optional)
(T/F) Parenthesis are mandatory for data aggregation
True
What does the resize function do?
It is used to extend or reduce the size of arrays
How is an unsigned extension performed?
Append ‘0’ to front of vector until ideal size reached
How is an unsigned reduction performed?
Remove frontmost bits until ideal size reached
How is a signed extension performed?
Append sign bit to front of vector until ideal size reached
How is a signed reduction performed?
Keep frontmost bit as sign bit, then remove bits afterwards until ideal size reached
What are the three types of type conversions?
1) Automatic
2) Type Cast
3) Type-conversion function
What is the purpose of behavioral architecture in VHDL
To show the output is derived from the inputs using
structured statements
What are the two types of statements for behavioral architecture?
1) Concurrent
2) Sequential
What type of circuits are concurrent statements useful for?
Combinational circuits
What is combinational logic?
When the output only depends on the current input (No memory)
What are the three purely concurrent statements?
WHEN,SELECT, GENERATE
WHEN EX: y <= “00” WHEN (a AND b) = “01” ELSE
“11” WHEN (a AND b) = “10” ELSE
“ZZ”; – high impedance
SELECT EX: WITH identifier SELECT
assignment_expression WHEN values,
assignment_value WHEN values,
……;
Does the when statement require all outputs to be specified?
No, but it is recommended
What does the unaffected keyword do?
It keeps the state of the signal the same
(T/F) Multiple values are accepted in SELECT statement, which can only be grouped with “|” or “TO”
True
(T/F) The SELECT statement requires that all input values be covered
True
(T/F) The generate statement is analogous to that of a sequential loop statement
True
What are the two types of generate statements?
1) Conditional
2) Unconditional
What is the FOR-GENERATE used for?
To create multiple instances of a section of code
(T/F) Range for generate statements is required to be dynamic
False (Static)
Where is a generic declared?
Before the port in the entity
(T/F) Generics are truly global
True
Are generics constant?
Yes
Are generics synthesizable?
Yes
What is the => operator used for?
Assigning values to array elements
What is the := operator used for?
Assigning values to a variable, constant, and initializing a signal
What is the <= operator used for?
Assigning values to a signal
(T/F) All logical operators have equal precedence
False (NOT has higher precedence)
What are the seven logical operators in VHDL?
1) NOT
2) OR
3) NOR
4) AND
5) NAND
6) XOR
7) XNOR
(T/F) Parenthesis can be used to control precedence of logical operators
True
Do unary operators take an operand from the left or right?
Right
Do binary operators take an operand from the left or right?
Both (TRICK QUESTION LOL)
abs(x) returns:
The absolute value of x
x REM y returns:
Remainder of x/y with sign of x
x MOD y returns:
Remainder of x/y with sign of y
What are the eight arithmetic operators?
1) + (add)
2) - (Subtract)
3) * (Multiply)
4) / (Divide)
5) ** (Exponentiation)
6) ABS (Absolute value)
7) REM (Remainder)
8) MOD (Modulo)
What are the six comparison operators?
1) Equals to (=)
2) Not equal (/=)
3) Less than (<)
4) Greater than (>)
5) Less than or equal (<=)
6) Greater than or equal (>=)
(T/F) The synthesizable predefined data types that support comparison operators are BIT, BIT_VECTOR, BOOLEAN, INTEGER, NATURAL, POSITIVE, CHARACTER, and STRING
True
Can bit vectors of different lengths be equal
No, different sized bit vectors never equal
What happens when doing comparisons of two differently sized bit vectors (Not including equal or unequal)
Leftmost bits of longer vector discarded
(T/F) When doing comparisons of bit vectors (Not including equal or unequal), if the vectors being compared become equal, the longer vector is considered larger than the other.
True
For all other SU-based types (not bit vector), are different sized vectors allowed in comparisons?
Yes
For all other SU-based types (not bit vector), what happens when the vectors are different sizes?
The shorter vector is resized to the length of the longer vector
What are the six shift operators in VHDL?
1) Shift left logic (SLL): positions on the right are filled with ‘0’s
2) Shift right logic (SRL) : positions on the left are filled with ‘0’s
3) Shift left arithmetic (SLA): rightmost bit is replicated on the right.
4) Shift right arithmetic (SRA): leftmost bit is replicated on the left
5) Rotate left (ROL): circular shift to the left
6) Rotate right (ROR): circular shift to the right
x = “01001”
1) y <= x SLL 2;
2) y <= x SLA 2;
3) y <= x SRL 3;
4) y <= x SRA 3;
5) y <= x ROL 2;
6) y <= x SRL -2;
1) “00100”
2) “00111”
3) “00001”
4) “00001”
5) “00101”
6) “00100”
(T/F) Reduction operators perform the binary logical operation on each individual bit in the string
True
What does T’Ascending return?
True if elements in T are in ascending order
What does T’Left return?
Leftmost value of T
What does T’POS(X) return?
Position number of X as an integer
What does T’RIGHTOF(x) return?
Value on the right of the position number X in T
(T/F) Predefined attributes can be applied to matrix types
True
(T/F) Data types can not be defined by the user
False
Syntax: TYPE type_name IS RANGE range_specifications;
or
TYPE type_name IS (type_values_list);
or
TYPE type_name IS ARRAY (range_specs) OF element_type;
How do you index a 1D x 1D array?
(x)(y) (x and y any integer index)
How do you index a 2D array?
(x, y) (x and y any integer index)
How do you index a 1D x 1D x 1D array?
(x)(y)(z) (x, y, and z any integer index)
How do you index a 3D array?
(x, y, z) (x, y, and z any integer index)
What are the main official VHDL packages?
“std”
“ieee”
How many packages are in the main official VHDL libraries?
Three in “std”.
Twelve in “ieee”.
What is one of the most important packages in VHDL? what does it do?
from the ieee library: “std_logic_1164”.
defines the nine-value type std_ulogic, and std_ulogic_vector.
How do you make a package visible to the compilier?
Declare it with library and use clauses.
library library_name;
use library_name. package_name. all;
What clauses are introduced automatically in VHDL projects?
library “std”, “work”;
use std.standard.all;
What are the most frequently used packages and libraries?
Package “standard” from the “std “library.
Library “work”
Package “std_logic/_1164”, from the “ieee” library
Package “numeric/_std”, from the “ieee” library
where is the “textio” package from and what is it used for?
from the library “std”
For dealing with text and files.
where is the “env” package from and what is it used for?
from the library “std”
For communication with the simulation environment.
What package can implement both fixed point and floating point arithmetic circuits?
Library ieee “fixed_float_types”
what does the package “numeric_bit” do
Introduces the types signed and unsigned and corresponding operators with bit as base type.
What does the package “numeric_bit_unsigned” do?
Package numeric_bit_unsigned: Contains operators and other functions for type bit_vector.
What does the package “numeric_bit_unsigned” do?
Package numeric_bit_unsigned: Contains operators and other functions for type bit_vector.
What library declaration do you use for arithmetic functions with Signed or Unsigned values?
“IEEE.NUMERIC_STD.ALL”
What does the package “Fixed_generic_pkg” do?
Defines the unsigned and signed fixed-point types ufixed and
sfixed, respectively,
What does the package “standard” do?
For implementing all sorts of logic and integer based arithmetic circuits but with major limitations; not recommended for arithmetic circuits and circuit ports
What does the package “std_logic_1164” do?
For Implementing any logic or arithmetic circuit (for the latter,
must associate with another package, like #7, #10, or #13)
What does the package “numeric_bit” do?
For implementing integer arithmetic circuits with type
unsigned or signed; has bit as base type
What does the package “numeric_std” do?
For implementing integer arithmetic circuits with type
unsigned or signed; has std_ulogic as base type
What does the package “numeric_bit_unsigned” do?
For doing unsigned operations with type bit_ vector
What does the package “numeric_std_unsigned” do?
For doing unsigned operations with type std_ulogic_vector
What does the packages “fixed_pkg”, “fixed_generic_pkg”, and “fixed_float_types” do?
For implementing fixed-point arithmetic circuits
What does the packages “fixed_float_types”, “float_pkg”, and “float_generic_pkg” do?
For implementing floating-point arithmetic circuits
What does the package “math_real” do?
For determining generic parameters (support not required for
synthesis, but might exist for real values that are static)
