Digital Systems T4

Question 1

The sNN is designed following:

Answer 1

The computer design methodology

Question 2

Which is more important in the BNNs as well as in ANNs?

Answer 2

The complexity (sophistication) of connections between neurons

Question 3

The sigmoid neuron weighs input evidence

Answer 3

True

Question 4

The perception weighs input evidence

Answer 4

True

Question 5

The perception below implement which binary function:
x1 –>-2
(3)–>
x2 –>-2

Answer 5

2-input NAND

Question 6

In the sigmoid neuron, if z is a large positive number then the output is

Answer 6

1

Question 7

In the learning/training phase of a NN the goal is to

Answer 7

Minimize the error

Question 8

The input layer of the proposed sNN has 9 input “neurons” (values. if we would increase the size of the image to 5x5 = 25 pixels, what will the number of the input layer “neurons” be?

Answer 8

25

Question 9

In a three-layer NN, the designer can modify the size of the

Answer 9

Hidden layer

Question 10

A positive weight value

Answer 10

Adds the value of the associated input

Question 11

The CORDIC hardware requires

Answer 11

Registers, CL shifters, and adder/subtractors

Question 12

Which of the following operations are not required in the CORDIC algorithm:

Answer 12

Multiplication

Question 13

In CORDIC rotation mode αi is selected so that

Answer 13

tan(αi) = di*2^(-i)

Question 14

For k-bits of precision, we need

Answer 14

k iterations

Question 15

A pseudo-rotation

Answer 15

Increases the magnitude of the vector

Question 16

In VHDL the WHEN-ELSE concurrent construct is the preferred way to implement a priority scheme

Answer 16

True

Question 17

A function can call another function, but not another task

Answer 17

True

Question 18

The verilog casex statement treats all z and x values as don’t cares

Answer 18

True

Question 19

A task can call another task and it can invoke a function

Answer 19

True

Question 20

Verilog casez statements treat only the z values as don’t cares

Answer 20

True

Question 21

What is the value of the even bit parity for “01101100”?

Answer 21

0

Question 22

The odd parity bit is the inverse of the even parity bit

Answer 22

True

Question 23

Which operation is used at the receiver to detect if there is a bit in error?

Answer 23

XOR between all bits received, INCLUDING the parity bit

Question 24

What is the value of the odd parity bit for “01101111”?

Answer 24

1

Question 25

which operation is used at the transmitter of data to compute the parity bit?

Answer 25

XOR between all bits to transmitted

Question 26

The difference in arrival time of the clock event (rising/falling edge) at the same location on the ship or on the PCB over a period of time is called:

Answer 26

Clock Jitter

Question 27

The minimum amount of time necessary for the input value to propagate from the moment it is sampled (clock event i.e. or rising/falling edge of the clock) to the output is called:

Answer 27

TcQ

Question 28

The propagation delay through the combinational logic circuit does affect Tmin

Answer 28

True

Question 29

Minimum amount of time the signal has to be stable at the input D of a DFF before the clock event is called:

Answer 29

The set up time

Question 30

The minimum amount of time the D input has to be stable after the clock event is called:

Answer 30

hold time

Question 31

The complexity of a CMOS gate is proportional to the number of inputs the

Answer 31

Longer the propagation delay

Question 32

TcQ is specified in a range of values. to calculate Tmin we use:

Answer 32

Its maximum value

Question 33

The difference in arrival time of the clock event (rising/falling edge) at different locations on the chip or on the PCB is called:

Answer 33

Clock Skew

Question 34

If the propagation delay through the shortest path is longer than the hold time, then

Answer 34

There is NO hold time violation

Question 35

The clock enables scheme below work _________ D -------------->|D Q|----------> Q | | E -------->| \ | | Clock -->| ) --|> Qbar| | / |________|

Answer 35

if we ensure that the E signal doesn't transition from low-to-high during the clock's high half-period

Question 36

To sensitive an OR gate the off-path inputs are tied to:

Answer 36

0

Question 37

An exhaustive test set is one which:

Answer 37

Applies at all inputs ALL possible combinations

Question 38

A stuck-at-1 circuit node or wire means that it is always reading:

Answer 38

Logic 1

Question 39

A complete test set is one that

Answer 39

Can detect ALL faults in a circuit

Question 40

To sensitize an AND gate sets the off-path inputs to:

Answer 40

1

Question 41

Test vectors that contain dont cares, i.e. x's

Answer 41

Can be replaced with test vectors that have the same values except for the bit positions that are x's

Question 42

To test if a DFF is stuck-at-1 we need to scan-in and out a bit sequence that contains at least a:

Answer 42

0

Question 43

A complete test is one that:

Answer 43

Has a complete fault coverage i.e. covers ALL faults

Question 44

To be able to test the NS- and Outputs-CLs:

Answer 44

The DFFs have to be fault-free, i.e. allow us to setup an arbitrary PS combined with a primary inputs TV

Question 45

To be detected, a fault has to be:

Answer 45

Stimulated, then its effect propagated towards an output, where it is finally observed

Question 46

A LFSR is used to generate stimuli (input test vectors)

Answer 46

True

Question 47

One of the disadvantages of the JTAG port and test protocol is:

Answer 47

It needs additional hardware resources, which are not used during normal/nominal operation

Question 48

a LFSR is used to generate an output signature. this is equivalent to a "compressed analysis" of the CUT outputs

Answer 48

True

Question 49

A linear feedback shift register generates a:

Answer 49

Pseudo-random sequence

Question 50

A BIST system:

Answer 50

Adds additional hardware resources which are not necessary during normal/nominal operation