Digital Systems T4 Flashcards
The sNN is designed following:
The computer design methodology
Which is more important in the BNNs as well as in ANNs?
The complexity (sophistication) of connections between neurons
The sigmoid neuron weighs input evidence
True
The perception weighs input evidence
True
The perception below implement which binary function:
x1 –>-2
(3)–>
x2 –>-2
2-input NAND
In the sigmoid neuron, if z is a large positive number then the output is
1
In the learning/training phase of a NN the goal is to
Minimize the error
The input layer of the proposed sNN has 9 input “neurons” (values. if we would increase the size of the image to 5x5 = 25 pixels, what will the number of the input layer “neurons” be?
25
In a three-layer NN, the designer can modify the size of the
Hidden layer
A positive weight value
Adds the value of the associated input
The CORDIC hardware requires
Registers, CL shifters, and adder/subtractors
Which of the following operations are not required in the CORDIC algorithm:
Multiplication
In CORDIC rotation mode αi is selected so that
tan(αi) = di*2^(-i)
For k-bits of precision, we need
k iterations
A pseudo-rotation
Increases the magnitude of the vector
In VHDL the WHEN-ELSE concurrent construct is the preferred way to implement a priority scheme
True
A function can call another function, but not another task
True
The verilog casex statement treats all z and x values as don’t cares
True
A task can call another task and it can invoke a function
True
Verilog casez statements treat only the z values as don’t cares
True
What is the value of the even bit parity for “01101100”?
0
The odd parity bit is the inverse of the even parity bit
True
Which operation is used at the receiver to detect if there is a bit in error?
XOR between all bits received, INCLUDING the parity bit
What is the value of the odd parity bit for “01101111”?
1
which operation is used at the transmitter of data to compute the parity bit?
XOR between all bits to transmitted
The difference in arrival time of the clock event (rising/falling edge) at the same location on the ship or on the PCB over a period of time is called:
Clock Jitter
The minimum amount of time necessary for the input value to propagate from the moment it is sampled (clock event i.e. or rising/falling edge of the clock) to the output is called:
TcQ
The propagation delay through the combinational logic circuit does affect Tmin
True
Minimum amount of time the signal has to be stable at the input D of a DFF before the clock event is called:
The set up time
The minimum amount of time the D input has to be stable after the clock event is called:
hold time
The complexity of a CMOS gate is proportional to the number of inputs the
Longer the propagation delay
TcQ is specified in a range of values. to calculate Tmin we use:
Its maximum value
The difference in arrival time of the clock event (rising/falling edge) at different locations on the chip or on the PCB is called:
Clock Skew
If the propagation delay through the shortest path is longer than the hold time, then
There is NO hold time violation
The clock enables scheme below work
_________
D ————–>|D Q|———-> Q
| |
E ——–>| \ | |
Clock –>| ) –|> Qbar|
| / |________|
if we ensure that the E signal doesn’t transition from low-to-high during the clock’s high half-period
To sensitive an OR gate the off-path inputs are tied to:
0
An exhaustive test set is one which:
Applies at all inputs ALL possible combinations
A stuck-at-1 circuit node or wire means that it is always reading:
Logic 1
A complete test set is one that
Can detect ALL faults in a circuit
To sensitize an AND gate sets the off-path inputs to:
1
Test vectors that contain dont cares, i.e. x’s
Can be replaced with test vectors that have the same values except for the bit positions that are x’s
To test if a DFF is stuck-at-1 we need to scan-in and out a bit sequence that contains at least a:
0
A complete test is one that:
Has a complete fault coverage i.e. covers ALL faults
To be able to test the NS- and Outputs-CLs:
The DFFs have to be fault-free, i.e. allow us to setup an arbitrary PS combined with a primary inputs TV
To be detected, a fault has to be:
Stimulated, then its effect propagated towards an output, where it is finally observed
A LFSR is used to generate stimuli (input test vectors)
True
One of the disadvantages of the JTAG port and test protocol is:
It needs additional hardware resources, which are not used during normal/nominal operation
a LFSR is used to generate an output signature. this is equivalent to a “compressed analysis” of the CUT outputs
True
A linear feedback shift register generates a:
Pseudo-random sequence
A BIST system:
Adds additional hardware resources which are not necessary during normal/nominal operation
