Digital Systems T1 Flashcards
The Verilog HDL is case-sensitive.
True
Which HDL description or model is a one-to-one match with the schematic diagram of a logic circuit?
Structural
The Verilog HDL has gate-level primitives defined in the language standard and recognized by the compiler/synthesizer.
True
The binary/logic operators in Verilog:
Use special characters
The first port in the port list of a Verilog gate level primitive is:
the one and only output
Does behavioral description give any hints about how the circuit should be implemented?
No
The statements in an always block are executed
whenever one or more signals in the sensitivity list change
The statements in a procedural block (always or initial in verilog) are executed
Sequentially
We can use functional description inside a procedural block
True
We can instantiate modules inside a procedural block
False
A test bench can be synthesized
Flase
A test bench has no input and outputs
True
Exhaustive verifications applies
All possible input combinations
The initial verilog procedural block is executed
Only once
The signals assigned a value inside a procedural block (always or initial verilog) have to declared of type
Reg
Which is the first deign step in the design flow?
Design entry/capture
Which type of languages can be describe both concurrent and sequential events?
hardware description languages (HDLs)
Which simulation type is more accurate i.e. models real logic circuits more accurate?
Timing simulation
which HDL was created first for documentation purposes?
VHDL
Which language was created first for modeling/simulation purposes?
Verilog
High impedance or tri-stated outputs are used to transfer data
From multiple sources to one destination
VHDL entity contains the component interface information
True
VHDL logic operators use:
Letters names, such as AND, OR, XOR, ect…
VHDL does NOT have built-in gate-level primitives
True
A VHDL component is comprised of
One entity and one or more architectures
All project files that contain descriptions belong automatically to the work library
True
The sensitivity list should contain all signals used inside the process on the right-hand-side of assignments
True
if-else and/or case statements can be nested
True
Behavioral description uses
Procedural statements
The statements in a VHDL process are executed
Sequentially
In Verilog the size of an instance using a parameterized module can be chosen
by providing a new value for the parameter(s) at the time of instantiation
In an RCA the carry-outs ripple (propagate) from the least significant bit (LSB) position to the most significant (MSB)
True
Multi-bit signals in verilog are described as
Vectors
In named (or explicit) association or (port mapping) the order of associations
Does NOT matter
To create paramterized descriptions using module instances
We need to use the GENERATE FOR loop/construct
To create generic descriptions using component instances
We can use the VHDL FOR GENERATE loop in the concurrent block of code
In a RCA the cout is known after all carries have propagated (rippled through) from:
the LSB to the MSB position
multi-bit signals in VHDL are described as:
Vectors
in VHDL a generic component can be resized from the default value(s) at instantiation time by
Providing another value for generics
In VHDL generic mapping maps
Generic to positive integer values
At instantiation time, the value of a parameter in verilog can be specified
In more than one way
The VHDL FOR GENERATE loop can only be used in a procedural block of code
False
The verilog GENERATE FOR loop can only be used in a concurrent block of code
True
The GENERATE FOR loop in verilog allows description of a circuit with arbitrary structure
False
the FOR GENERATE loop in VHDL allows the description with a repetitive (period) structure
True
A 2-variable function can be implemented using 4to1mux by
Connecting the 2-vairables/inputs to the data of the mux
In the implementation of a function (CL circuit) we can combine gates and muxes
True
Expansion by different variables/intputs may result in co-factors of different complexities
True
Any binary function can be implemented
True
Higher-order multiplexers can be built using lower order multiplexers. ultimately at the lowest level of the implementation one would use 2-to-1 muxes
True
In a FPGA LUT the data inputs of the multiplexer are driven by:
Values stored in storage elements
The application of Shannon’s expansion theorem involves the following steps:
1 - Expansion - if necessary to produce terms that contain the true and complemented values of the expansion variable
2 - Re-arrangement of the function form
3 - Simplification of the co-factors - if necessary
True
a not gate can be implemented using 2to1mux by:
Connecting the NOT input to the select input of the mux and its data input 0 connected to 1 and 1 connected to 0 respectively
If we expand a function by 2 variables, we need at least a:
4to1mux
The canonical form of function is
The SOP of all the terms for which the function is 1
