Digital Systems T1 Flashcards
The Verilog HDL is case-sensitive.
True
Which HDL description or model is a one-to-one match with the schematic diagram of a logic circuit?
Structural
The Verilog HDL has gate-level primitives defined in the language standard and recognized by the compiler/synthesizer.
True
The binary/logic operators in Verilog:
Use special characters
The first port in the port list of a Verilog gate level primitive is:
the one and only output
Does behavioral description give any hints about how the circuit should be implemented?
No
The statements in an always block are executed
whenever one or more signals in the sensitivity list change
The statements in a procedural block (always or initial in verilog) are executed
Sequentially
We can use functional description inside a procedural block
True
We can instantiate modules inside a procedural block
False
A test bench can be synthesized
Flase
A test bench has no input and outputs
True
Exhaustive verifications applies
All possible input combinations
The initial verilog procedural block is executed
Only once
The signals assigned a value inside a procedural block (always or initial verilog) have to declared of type
Reg
Which is the first deign step in the design flow?
Design entry/capture
Which type of languages can be describe both concurrent and sequential events?
hardware description languages (HDLs)
Which simulation type is more accurate i.e. models real logic circuits more accurate?
Timing simulation
which HDL was created first for documentation purposes?
VHDL
Which language was created first for modeling/simulation purposes?
Verilog
High impedance or tri-stated outputs are used to transfer data
From multiple sources to one destination
VHDL entity contains the component interface information
True
