Digital Systems T2

Question 1

If we add two numbers of the same sign and the sign of the result is opposite of the sign did overflow occur?

Answer 1

Yes

Question 2

the zero (Z) status bit is 1 if the result is:

Answer 2

0

Question 3

For 2sC represented numbers, the negative status bit (N) is 1 if the MSbit of the result is:

Answer 3

1

Question 4

A Shift right arithmetic

Answer 4

Replicates the MSbit to maintain the sing of the operand in 2sC

Question 5

A rotate left through carry (RLC) allows us to transfer into the carry the value

Answer 5

of the MSbit of the operand

Question 6

A Verilog task is similar to a procedural in a high-level programming language

Answer 6

True

Question 7

Which type of operation is NOT implemented in an ALU?

Answer 7

Storage

Question 8

We can shift or rotate by ONE or MORE positions

Answer 8

True

Question 9

The ALU outputs the results of ONE and ONLY one operation at a time

Answer 9

True

Question 10

The C and the V values are not relevant for

Answer 10

Logical Operations

Question 11

The VHDL conditional signal assignment is like the procedural if-else can be used in the concurrent block of code

Answer 11

True

Question 12

The VHDL select signal assignment is like the procedural case but can be used in the concurrent block of code

Answer 12

True

Question 13

The verilog conditional operator can be used in both concurrent and procedural blocks of code

Answer 13

True

Question 14

The verilog conditional operator can be nested

Answer 14

True

Question 15

Which description results in a more efficient implementation?

Answer 15

Structural (Hierarchical)

Question 16

To write an arbitrary value into a register, which of the following control signals can we activate?

Answer 16

Load

Question 17

The attribute signal_name’event detects a change in signal name, which can be either low-to-high or high-to-low

Answer 17

True

Question 18

The keyword ‘negedge’ in Verilog detects the occurrence of

Answer 18

A falling edge of a signal

Question 19

The DFF is an

Answer 19

Edge triggered device

Question 20

The user of a memory starts a memory access cycle by first providing the address of the location to be accessed

Answer 20

True

Question 21

A ROM loses its content when powered down

Answer 21

False

Question 22

A m-bit wide address value can access

Answer 22

2^(m) locations

Question 23

The Din and WR input ports are necessary in a

Answer 23

RAM

Question 24

A RAM loses its content when powered down

Answer 24

True

Question 25

In both ROM and RAM memories

Answer 25

Locations are accessed with the same access times

Question 26

during either READ or WRITE cycle the user of a memory has to provide an address

Answer 26

True

Question 27

The content and/or organization of data memory is described by memory (address)

Answer 27

True

Question 28

The address value 10xxx110 points to

Answer 28

Eight locations

Question 29

A Special Function Register (SFR) can be designed using the FSM design methodology

Answer 29

True

Question 30

The parallel output value of a SFR is

Answer 30

Equal to the Present State value i.e, the outputs of the registers’s DFFs

Question 31

The registers of a register file share

Answer 31

Control signals and inputs and output ports

Question 32

Which IS or ISA implemented only a few tens of instructions and each instruction completes a “simple” operation

Answer 32

RISC

Question 33

The computer design methodology divides the design into two major function blocks: DP and CU

Answer 33

True

Question 34

how many address locations does this address value reference: 1x0x?

Answer 34

4

Question 35

which of the following code representations is NOT (easily) readable?

Answer 35

Machine language

Question 36

In dxp RISC the MAeffective is calculated as the sum of an address value and a register value

Answer 36

True

Question 37

The ISA represents the design interface between

Answer 37

The logic designer and software designer (programmer)

Question 38

Aside from the IS the ISA contains information about the organization of storage

Answer 38

True

Question 39

In which functional block is data being processed, i.e. stored, transferred, and manipulated?

Answer 39

DP

Question 40

Which functional block is responsible for the sequencing of events in the CPU (DP&CU)?

Answer 40

CU

Question 41

Which special function control register holds the address of the next instruction word (IW) to be fetched?

Answer 41

PC

Question 42

An ASM chart STATE BOX captures…

Answer 42

Concurrent events

Question 43

The Operation Code (OpCode) field in the dxpRISC IW determines

Answer 43

The operation to be performed

Question 44

An ASM chart binary conditional has

Answer 44

One input and two outputs

Question 45

Which special function control register holds the instruction word (IW) of the current instruction?

Answer 45

IR

Question 46

A (hardware) stack is a

Answer 46

Last-infist-out (LIFO) memory organization

Question 47

To access memory-mapped I/O-Ps one uses

Answer 47

LD and ST instructions

Question 48

Which of the following are I/O-Ps?

Answer 48

PB1 and SW

Question 49

Which of the following values are NOT used to calculate the effective memory address for LD and ST?

Answer 49

PC

Question 50

To access separate mapped I/O-Ps one uses

Answer 50

IN and OUT instructions

Question 51

Which are the two pieces of information that the CU needs to determine what cycle it has to execute?

Answer 51

OpCode and current MC

Question 52

The process during which a binary IW (machine language instruction) is converted into a assembly language instruction is called

Answer 52

Disassembly

Question 53

The CST is the design interface between the design of the DP and the CU

Answer 53

True

Question 54

Which design tool captures BOTH sequential and concurrent events?

Answer 54

ASM chart

Question 55

A JUMP instruction is a control flow instruction which can alter the sequential flow of instruction execution

Answer 55

True

Question 56

The dxpRISC data path is described

Answer 56

Structurally

Question 57

Instruction cycles (ICs) are in the dxpRISC are:

Answer 57

Variable length i.e, take different numbers of machine cycles

Question 58

The Quartus *mif.file contains:

Answer 58

The values with which memory is initialized

Question 59

The Instruction Decode (ID) machine cycle is necessary to

Answer 59

Transfer IW to the CU and allow it to decode it

Question 60

in the context of the DE0-Nano Board, the LEDs are

Answer 60

Output peripherals