Digital Systems T2 Flashcards
If we add two numbers of the same sign and the sign of the result is opposite of the sign did overflow occur?
Yes
the zero (Z) status bit is 1 if the result is:
0
For 2sC represented numbers, the negative status bit (N) is 1 if the MSbit of the result is:
1
A Shift right arithmetic
Replicates the MSbit to maintain the sing of the operand in 2sC
A rotate left through carry (RLC) allows us to transfer into the carry the value
of the MSbit of the operand
A Verilog task is similar to a procedural in a high-level programming language
True
Which type of operation is NOT implemented in an ALU?
Storage
We can shift or rotate by ONE or MORE positions
True
The ALU outputs the results of ONE and ONLY one operation at a time
True
The C and the V values are not relevant for
Logical Operations
The VHDL conditional signal assignment is like the procedural if-else can be used in the concurrent block of code
True
The VHDL select signal assignment is like the procedural case but can be used in the concurrent block of code
True
The verilog conditional operator can be used in both concurrent and procedural blocks of code
True
The verilog conditional operator can be nested
True
Which description results in a more efficient implementation?
Structural (Hierarchical)
To write an arbitrary value into a register, which of the following control signals can we activate?
Load
The attribute signal_name’event detects a change in signal name, which can be either low-to-high or high-to-low
True
The keyword ‘negedge’ in Verilog detects the occurrence of
A falling edge of a signal
The DFF is an
Edge triggered device
The user of a memory starts a memory access cycle by first providing the address of the location to be accessed
True
A ROM loses its content when powered down
False
A m-bit wide address value can access
2^(m) locations
The Din and WR input ports are necessary in a
RAM
A RAM loses its content when powered down
True
In both ROM and RAM memories
Locations are accessed with the same access times
during either READ or WRITE cycle the user of a memory has to provide an address
True
The content and/or organization of data memory is described by memory (address)
True
The address value 10xxx110 points to
Eight locations
A Special Function Register (SFR) can be designed using the FSM design methodology
True
The parallel output value of a SFR is
Equal to the Present State value i.e, the outputs of the registers’s DFFs
The registers of a register file share
Control signals and inputs and output ports
Which IS or ISA implemented only a few tens of instructions and each instruction completes a “simple” operation
RISC
The computer design methodology divides the design into two major function blocks: DP and CU
True
how many address locations does this address value reference: 1x0x?
4
which of the following code representations is NOT (easily) readable?
Machine language
In dxp RISC the MAeffective is calculated as the sum of an address value and a register value
True
The ISA represents the design interface between
The logic designer and software designer (programmer)
Aside from the IS the ISA contains information about the organization of storage
True
In which functional block is data being processed, i.e. stored, transferred, and manipulated?
DP
Which functional block is responsible for the sequencing of events in the CPU (DP&CU)?
CU
Which special function control register holds the address of the next instruction word (IW) to be fetched?
PC
An ASM chart STATE BOX captures…
Concurrent events
The Operation Code (OpCode) field in the dxpRISC IW determines
The operation to be performed
An ASM chart binary conditional has
One input and two outputs
Which special function control register holds the instruction word (IW) of the current instruction?
IR
A (hardware) stack is a
Last-infist-out (LIFO) memory organization
To access memory-mapped I/O-Ps one uses
LD and ST instructions
Which of the following are I/O-Ps?
PB1 and SW
Which of the following values are NOT used to calculate the effective memory address for LD and ST?
PC
To access separate mapped I/O-Ps one uses
IN and OUT instructions
Which are the two pieces of information that the CU needs to determine what cycle it has to execute?
OpCode and current MC
The process during which a binary IW (machine language instruction) is converted into a assembly language instruction is called
Disassembly
The CST is the design interface between the design of the DP and the CU
True
Which design tool captures BOTH sequential and concurrent events?
ASM chart
A JUMP instruction is a control flow instruction which can alter the sequential flow of instruction execution
True
The dxpRISC data path is described
Structurally
Instruction cycles (ICs) are in the dxpRISC are:
Variable length i.e, take different numbers of machine cycles
The Quartus *mif.file contains:
The values with which memory is initialized
The Instruction Decode (ID) machine cycle is necessary to
Transfer IW to the CU and allow it to decode it
in the context of the DE0-Nano Board, the LEDs are
Output peripherals
