Day 6 Flashcards
Risc architecture
have on operation per instruction. majority of smart phones and tablets run on processors using RISC based ARM architecture
ARM registers
arranged in 2 to 16 banks of 16 registers. prevents having to save the contents of the registers when dealing with interrupts or system calls.
General-Purpose Registers (GPR)
may be directly accessed by the programmer for any purpose.
ARM General purpose registers
R0 Accumulator R1 Base R2 Counter R3 Data R4 Source R5 Destination R11 Base Pointer
Segment Register
special purpose registers used as base locations for program instructions, data, and stack.
What are the Arm’s two segment registers?
SP (R13) Stack pointer
LR (R14) Link Register - stores the return address for subroutines
Control and status registers
special purpose registers that hold information about the most recently performed ALU operation, memory alignment, endianness, enabling and disabling of interrupts, and set processor-operating mode.
ARM status and control registers
PC (control) Program counter - pointer to next instruction in memory
CPSR (Status) Current Program Status Register- holds the condition of the program.
ARM modes of operation
dictate which instruction and architectural features are available to a process.
User (usr)
user mode is the default ARM program execution state and is used for executing most application programs.
System (sys)
Runs privileged OS tasks (routine OS business)
FIQ
used when handling high priority (fast) interrupts.
IRQ
Used when handling low priority (normal) interrupts.
Supervisor (svc)
protected mode for the OS (system calls)
Abort
used to handle memory access violations
Undef
used to handle undefined or unimplemented instructions
Secure Monitor (mon)
used to transfer control from non-secure to secure and vice versa by the processor.
ARM privilege levels
hardware enforced permissions to ensure system security through process isolation.
PL0 - user mode indicates an unprivileged execute security state where many features of the architecture are unavailable
PL1 - used by all other modes of operation, beside user, where system software is executed.
ARM Instructions
has instructions for moving data betwen memory and the CPU, performing arithmetic functions, making boolean decisions, executing flow control, and controlling the stack
Data movement instructions
used to move data from register-to-register, register-to-memory, and memory-to-register.
Operand addressing mode
defines where to find the data (operand) to be manipulated by the instruction (opcode).
