Day 6

Question 1

Risc architecture

Answer 1

have on operation per instruction. majority of smart phones and tablets run on processors using RISC based ARM architecture

Question 2

ARM registers

Answer 2

arranged in 2 to 16 banks of 16 registers. prevents having to save the contents of the registers when dealing with interrupts or system calls.

Question 3

General-Purpose Registers (GPR)

Answer 3

may be directly accessed by the programmer for any purpose.

Question 4

ARM General purpose registers

Answer 4

R0 Accumulator
R1 Base
R2 Counter
R3 Data
R4 Source
R5 Destination 
R11 Base Pointer

Question 5

Segment Register

Answer 5

special purpose registers used as base locations for program instructions, data, and stack.

Question 6

What are the Arm’s two segment registers?

Answer 6

SP (R13) Stack pointer

LR (R14) Link Register - stores the return address for subroutines

Question 7

Control and status registers

Answer 7

special purpose registers that hold information about the most recently performed ALU operation, memory alignment, endianness, enabling and disabling of interrupts, and set processor-operating mode.

Question 8

ARM status and control registers

Answer 8

PC (control) Program counter - pointer to next instruction in memory
CPSR (Status) Current Program Status Register- holds the condition of the program.

Question 9

ARM modes of operation

Answer 9

dictate which instruction and architectural features are available to a process.

Question 10

User (usr)

Answer 10

user mode is the default ARM program execution state and is used for executing most application programs.

Question 11

System (sys)

Answer 11

Runs privileged OS tasks (routine OS business)

Question 12

FIQ

Answer 12

used when handling high priority (fast) interrupts.

Question 13

IRQ

Answer 13

Used when handling low priority (normal) interrupts.

Question 14

Supervisor (svc)

Answer 14

protected mode for the OS (system calls)

Question 15

Abort

Answer 15

used to handle memory access violations

Question 16

Undef

Answer 16

used to handle undefined or unimplemented instructions

Question 17

Secure Monitor (mon)

Answer 17

used to transfer control from non-secure to secure and vice versa by the processor.

Question 18

ARM privilege levels

Answer 18

hardware enforced permissions to ensure system security through process isolation.
PL0 - user mode indicates an unprivileged execute security state where many features of the architecture are unavailable
PL1 - used by all other modes of operation, beside user, where system software is executed.

Question 19

ARM Instructions

Answer 19

has instructions for moving data betwen memory and the CPU, performing arithmetic functions, making boolean decisions, executing flow control, and controlling the stack

Question 20

Data movement instructions

Answer 20

used to move data from register-to-register, register-to-memory, and memory-to-register.

Question 21

Operand addressing mode

Answer 21

defines where to find the data (operand) to be manipulated by the instruction (opcode).