CSCI 223 Test 1 Flashcards
1
Q
source program
A
created with an editor and saved in a text file (extension .c)
2
Q
how many bits are in a byte
A
8
3
Q
files that consist exclusively of ASCII characters are known as ?; all other files are known as
A
text files; binary files
4
Q
? goes into the preprocessor and ? comes out
A
source program (text); modified source program (text)
5
Q
? goes into the compiler and ? comes out
A
modified source program (text); assembly program (text)
6
Q
? goes into the assembler and ? comes out
A
assembly program (text); object file (binary)
7
Q
? goes into the linker and ? comes out
A
object file (binary); executable file (binary)
8
Q
what programs perform the four phases of preprocessing, compiling, assembling, and linking?
A
preprocessor, assembler, compiler, linker
9
Q
Why do we need to understand how compilation systems work?
A
to optimize program performance, understand link-time errors, and avoid security holes
10
Q
assembly language definition
A
low-level programming language which is a human readable, textual representation of machine code
11
Q
assembly language facts
A
each statement corresponds to a single machine code; each assembly language is specific to a particular processor architecture (ISA); it contains a lot of hardware info
12
Q
ISA
A
Instruction Set Architecture: interface b/w software and hardware (e.g. x86, ARM, MIPS, …); assembly language is very important to the ISA
13
Q
what translates high level languages to low level languages?
A
the compiler
14
Q
examples of high level programming
A
C/C++, Java, …
15
Q
examples of low level programming
A
x86, ARM, MIPS, …
16
Q
a system is made up of
A
hardware and software
17
Q
software is made up of
A
application programs and the operating system
18
Q
hardware is made up of
A
processor, memory, I/O devices, etc.
19
Q
ALU
A
arithmetic logic unit
20
Q
what is the fastest yet smallest memory space?
A
the register file (inside the CPU)
21
Q
onchip memory versus offchip memory
A
offchip: outside CPU and onchip: inside CPU (e.g. main memory is offchip; cache, register file is onchip)
22
Q
onchip memory has (faster/slower) access time than main memory
A
faster
23
Q
memory hierarchy generalization
A
smaller, faster, and costlier (per byte) storage devices at the top to larger, slower, and cheaper (per byte) storage devices at the bottom
24
Q
memory hierarchy L0
A
registers
25
memory hierarchy L1
L1 cache (SRAM)
26
memory hierarchy L2
L2 cache (SRAM)
27
memory hierarchy L3
L3 cache (SRAM)
28
memory hierarchy L4
main memory (DRAM)
29
memory hierarchy L5
local secondary storage (local disks)
30
memory hierarchy L6
remote secondary storage (distributed file systems, web servers)
31
between levels ? and ? in the memory hierarchy is where we can differentiate onchip (above) and offchip (below)
L3 and up is onchip, L4 and below is offchip
32
main memory holds ? retrieved from local disks
disk blocks
33
cache holds ? retrieved from memory
cache lines
34
CPU registers hold ? retrieved from cache memory
words
35
why does the cache matter?
for performance; performance depends on access patterns
36
binary representation
everything is represented as a sequence of binary numbers in digital systems (0 or 1)
37
byte
8 bit chunk; smallest data access unit
38
each byte has a ? memory address
unique
39
machine code views memory as ?
a very large array of bytes (referred to as virtual memory)
40
widely-used numeral systems
decimal (base 10), *hexadecimal/hex (base 16)*, octal (base 8), and binary (base 2)
41
how to convert from decimal to hexadecimal
divide by 16, read the remainders from bottom to top
42
how to convert from decimal to binary
divide by 2, use the remainders from bottom to top (should be 0s and 1s)
43
how to convert from hexadecimal to decimal
label the positions from right to left as 0, 1, 2, ... and multiply the number by 16^? and add the results together
44
how to convert from binary to decimal
label the positions from right to left as 0, 1, 2, ... and multiply the number by 2^? and add the results together
45
how to convert from binary to hexadecimal or binary to hexadecimal
use the chart
46
0x0
0000
47
0x1
0001
48
0x2
0010
49
0x3
0011
50
0x4
0100
51
0x5
0101
52
0x6
0110
53
0x7
0111
54
0x8
1000
55
0x9
1001
56
0xA
1010
57
0xB
1011
58
0xC
1100
59
0xD
1101
60
0xE
1110
61
0xF
1111
62
Little Endian ordering
least significant byte (furthest to the right) has lowest address
63
pointer
a variable whose content is a memory address
64
how to declare a pointer
int *p;
65
and chart
& 0 1
0 0 0
1 0 1
66
or chart
| 0 1
0 0 1
1 1 1
67
not chart
0 1
| ~ 1 0
68
exclusive or chart
^ 0 1
0 0 1
1 1 0
69
logical operations in C (logical and, logical or, logical not)
&&, ||, !
70
view zero as (true/false) and anything nonzero as (true/false)
false, true
71
for logical or, you want to place the more likely term to be (0 or 1) first
1
72
for logical and, you want to place the more likely term to be (0 or 1) first
0
73
left shift x << y will
shift bit-vector x left by y positions: throw away extra bits on left and will with 0's on the right; similar to multiplication by 2^x
74
right shift x >> y will
shift bit-vector x right by y positions; similar to division by power of 2
75
logical right shift
fill with zero's on the left
76
arithmetic right shift
replicate the most significant bit to the right on the left
77
ISA
Instruction Set Architecture - interface between software and hardware
78
ISA is considered (micro/macro)architecture
macroarchitecture
79
microarchitecture
implementation of macroarchitecture; not visible to software; can vary as long as it satisfies the macroarchitecture
80
system stack: software
problem, algorithm, program
81
system stack: hardware
microarchitecture, circuits, transistors
82
Moore's Law
transistor counts double every 18-24 months on a single chip (means the performance will double)
83
PC (program counter)
contains the address of the next instruction to execute; called "%eip" (IA32) or "%rip" (x86-64)
84
register file
collection of registers; used to store heavily used program data
85
condition codes
store status information about most recent arithmetic operation; used for conditional branching
86
memory
byte addressable array; code, user data, some OS data; includes stack used to support procedures
87
three basic operations of machine instructions
1. arithmetic and logic operation (ALU)
2. memory operation (AKA data movement)
3. control-flow operation
88
x86 is a (CISC/RISC) type
CISC
89
CISC
Complex Instruction Set Computers; large number of instructions, varying instruction length, various addressing formats, complex compiler and hardware, compact code size
90
RISC
Reduced Instruction Set Computers; smaller number of instructions, fixed instruction length, only a few addressing formats, simpler compiler and hardware, larger code size
91
assembly data types
integer data (including memory address), floating point data; no aggregate types such as arrays or structures, just continuously allocated bytes in memory
92
assembly operations
perform arithmetic/logical function on register or memory data, transfer data b/w memory and register, transfer control
93
disassembler
useful tool for examining object code; analyses bit pattern of series of instructions, produces approximate rendition of assembly code, can be run on either a.out (complete executable) or .o file
94
x86-64 Integer registers
supposed to contain integer value or memory address; can reference low-order 4 bytes; controlled by compiler; 16 registers
95
IA32 integer registers
8 integer registers (first 6 - general purpose, %esp: stack pointer, %ebp: base pointer); can reference low-order 1 byte, 2 bytes, and 4 bytes; 16-bit registers with backwards compatibility
96
operand types
immediate, register, memory
97
immediate operand type
constant integer data; like C constant, but prefixed w/ '$'; encoded with 1, 2, or 4 bytes
98
register operand type
one of 16 integer registers; %rsp reserved for special use; others have special uses for particular instructions
99
memory operand type
8 consecutive bytes of memory at address given by register; various other "address modes"
100
simple memory addressing modes
Normal: (R) Mem[Reg[R]]
Diplacement: D(R) Mem[Reg[R]+[D]]
101
complete memory addressing modes
most general form: D(Rb, Ri, S)
Mem[Reg[Rb] + S*Reg[Ri]+D]
where D = constant "displacement", Rb = base register, Ri = index register, and S = scale
102
special memory address cases
(Rb, Ri) > Mem[Reg[Rb]+Reg[Ri]]
D(Rb, Ri) > Mem[Reg[Rb]+Reg[Ri]+D]
(Rb, Ri, S) > Mem[Reg[Rb]+S*Reg[Ri]]
103
ALU two operand instructions (Src, Dest)
addq (+), subq (-), imulq (*), salq (<>), shrq (>>), xorq (^), andq (&), orq (|)
104
ALU one operand instructions (Dest)
incq (Dest+1), decq (Dest-1), negq (-Dest), notq (~Dest)
105
leaq Src, Dest
pure ALU instruction that simply computes memory addresses (in contrast to movq, which accesses memory); Src is address mode expression, set Dst to address denoted by expression; useful for computing addresses without a memory reference and computing arithmetic instructions fo the form x+k*y
106
control flow instructions: processor state
info about currently executing program:
| temporary data, location of runtime stack, location of current code control point, status of recent tests
107
condition codes for single bit registers
CF - Carry Flag (for unsigned), ZF - Zero Flag, SF - Sign Flag (for unsigned), OF - Overflow Flag (for signed)
108
implicitly set condition codes by arithmetic operations
e.g. addl Src, Dest //t = a+b
CF set if carry out most significant bit (used for unsigned comparisons)
ZF set if t==0
SF set if t<0 (as signed)
OF set if two's complement (signed overflow): (a>0 && b<0 && (a-b)<0) || (a<0 && b>0 && (a-b) > 0)
109
condition codes explicit setting by Test instruction
testl/testq Src2, Src1
testl b,a like computing a&b without setting destination
sets condition codes based on value of Src1 & Src2
useful to have one of the operands be a mask
ZF set when a&b == 0
SF set when a&b < 0
110
C data type char size
1 byte
111
C data type short size
2 bytes
112
C data type int size
4 bytes
113
C data type long size
4 bytes
114
C data type long long size
8 bytes
115
C data type float size
4 bytes
116
C data type double
8 bytes
117
C data type long double size
8 bytes
118
C data type pointer size
4 bytes
119
condition codes explicit setting by Compare instruction
cmpl/cmpq Src2, Src1
cmpl b,a like computing a-b (subtraction) without setting destination
CF set if carry out from most significant big (for unsigned)
ZF set if a==b
SF set if (a-b)<0 (as unsigned)
OF set if two's complement (signed) overflow
120
SetX instructions
set a single byte based on combo of condition codes
| one of 8 addressable byte registers; does not alter remaining 3 bytes; typically use movzbl to finish job
121
jX instructions
jump to a different part of the code depending on condition codes
122
jump target
in assembly code - symbolic labels
| in machine binary - PC relative, absolute
123
difference between while, do-while, and for loops
do while will run at least once
while checks condition first
for loop initializes, tests, and updates in condition
124
mechanisms in procedures
passing control (to beginning of procedure code or back to return point), passing data (procedure arguments, return value), memory management (allocate during procedure execution, de-allocate upon return)
all implemented with machine instructions; x86-64 implementation of a procedure only uses those mechanisms required
125
x86-64 stack
region of memory managed with stack discipline (FILO), grows toward lower addresses, register %rsp contains the address of the top of the stack (lowest address)
126
x86-64 stack: push
pushq Src (Dest implicit > top of stack)
- fetch (read) operant at Src
- decrement %rsp by 8
- write operand at address given by %rsp
127
x86-64 stack: pop
popq Dest
- read value at address given by %rsp
- increment %rsp by 8
- store value at Dest (must be register)
