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Fall 2017 > CSCI 223 Test 1 > Flashcards

CSCI 223 Test 1 Flashcards

1
Q

source program

A

created with an editor and saved in a text file (extension .c)

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2
Q

how many bits are in a byte

A

8

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3
Q

files that consist exclusively of ASCII characters are known as ?; all other files are known as

A

text files; binary files

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4
Q

? goes into the preprocessor and ? comes out

A

source program (text); modified source program (text)

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5
Q

? goes into the compiler and ? comes out

A

modified source program (text); assembly program (text)

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6
Q

? goes into the assembler and ? comes out

A

assembly program (text); object file (binary)

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7
Q

? goes into the linker and ? comes out

A

object file (binary); executable file (binary)

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8
Q

what programs perform the four phases of preprocessing, compiling, assembling, and linking?

A

preprocessor, assembler, compiler, linker

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9
Q

Why do we need to understand how compilation systems work?

A

to optimize program performance, understand link-time errors, and avoid security holes

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10
Q

assembly language definition

A

low-level programming language which is a human readable, textual representation of machine code

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11
Q

assembly language facts

A

each statement corresponds to a single machine code; each assembly language is specific to a particular processor architecture (ISA); it contains a lot of hardware info

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12
Q

ISA

A

Instruction Set Architecture: interface b/w software and hardware (e.g. x86, ARM, MIPS, …); assembly language is very important to the ISA

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13
Q

what translates high level languages to low level languages?

A

the compiler

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14
Q

examples of high level programming

A

C/C++, Java, …

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15
Q

examples of low level programming

A

x86, ARM, MIPS, …

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16
Q

a system is made up of

A

hardware and software

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17
Q

software is made up of

A

application programs and the operating system

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18
Q

hardware is made up of

A

processor, memory, I/O devices, etc.

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19
Q

ALU

A

arithmetic logic unit

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20
Q

what is the fastest yet smallest memory space?

A

the register file (inside the CPU)

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21
Q

onchip memory versus offchip memory

A

offchip: outside CPU and onchip: inside CPU (e.g. main memory is offchip; cache, register file is onchip)

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22
Q

onchip memory has (faster/slower) access time than main memory

A

faster

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23
Q

memory hierarchy generalization

A

smaller, faster, and costlier (per byte) storage devices at the top to larger, slower, and cheaper (per byte) storage devices at the bottom

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24
Q

memory hierarchy L0

A

registers

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25
Q

memory hierarchy L1

A

L1 cache (SRAM)

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26
Q

memory hierarchy L2

A

L2 cache (SRAM)

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27
Q

memory hierarchy L3

A

L3 cache (SRAM)

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28
Q

memory hierarchy L4

A

main memory (DRAM)

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29
Q

memory hierarchy L5

A

local secondary storage (local disks)

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30
Q

memory hierarchy L6

A

remote secondary storage (distributed file systems, web servers)

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31
Q

between levels ? and ? in the memory hierarchy is where we can differentiate onchip (above) and offchip (below)

A

L3 and up is onchip, L4 and below is offchip

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32
Q

main memory holds ? retrieved from local disks

A

disk blocks

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33
Q

cache holds ? retrieved from memory

A

cache lines

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34
Q

CPU registers hold ? retrieved from cache memory

A

words

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35
Q

why does the cache matter?

A

for performance; performance depends on access patterns

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36
Q

binary representation

A

everything is represented as a sequence of binary numbers in digital systems (0 or 1)

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37
Q

byte

A

8 bit chunk; smallest data access unit

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38
Q

each byte has a ? memory address

A

unique

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39
Q

machine code views memory as ?

A

a very large array of bytes (referred to as virtual memory)

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40
Q

widely-used numeral systems

A

decimal (base 10), hexadecimal/hex (base 16), octal (base 8), and binary (base 2)

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41
Q

how to convert from decimal to hexadecimal

A

divide by 16, read the remainders from bottom to top

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42
Q

how to convert from decimal to binary

A

divide by 2, use the remainders from bottom to top (should be 0s and 1s)

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43
Q

how to convert from hexadecimal to decimal

A

label the positions from right to left as 0, 1, 2, … and multiply the number by 16^? and add the results together

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44
Q

how to convert from binary to decimal

A

label the positions from right to left as 0, 1, 2, … and multiply the number by 2^? and add the results together

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45
Q

how to convert from binary to hexadecimal or binary to hexadecimal

A

use the chart

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46
Q

0x0

A

0000

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47
Q

0x1

A

0001

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48
Q

0x2

A

0010

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49
Q

0x3

A

0011

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50
Q

0x4

A

0100

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51
Q

0x5

A

0101

52
Q

0x6

A

0110

53
Q

0x7

A

0111

54
Q

0x8

A

1000

55
Q

0x9

A

1001

56
Q

0xA

A

1010

57
Q

0xB

A

1011

58
Q

0xC

A

1100

59
Q

0xD

A

1101

60
Q

0xE

A

1110

61
Q

0xF

A

1111

62
Q

Little Endian ordering

A

least significant byte (furthest to the right) has lowest address

63
Q

pointer

A

a variable whose content is a memory address

64
Q

how to declare a pointer

A

int *p;

65
Q

and chart

A

& 0 1
0 0 0
1 0 1

66
Q

or chart

A

0 1
0 0 1
1 1 1

67
Q

not chart

A

0 1

~ 1 0

68
Q

exclusive or chart

A

^ 0 1
0 0 1
1 1 0

69
Q

logical operations in C (logical and, logical or, logical not)

A

&&, ||, !

70
Q

view zero as (true/false) and anything nonzero as (true/false)

A

false, true

71
Q

for logical or, you want to place the more likely term to be (0 or 1) first

A

1

72
Q

for logical and, you want to place the more likely term to be (0 or 1) first

A

0

73
Q

left shift x &laquo_space;y will

A

shift bit-vector x left by y positions: throw away extra bits on left and will with 0’s on the right; similar to multiplication by 2^x

74
Q

right shift x&raquo_space; y will

A

shift bit-vector x right by y positions; similar to division by power of 2

75
Q

logical right shift

A

fill with zero’s on the left

76
Q

arithmetic right shift

A

replicate the most significant bit to the right on the left

77
Q

ISA

A

Instruction Set Architecture - interface between software and hardware

78
Q

ISA is considered (micro/macro)architecture

A

macroarchitecture

79
Q

microarchitecture

A

implementation of macroarchitecture; not visible to software; can vary as long as it satisfies the macroarchitecture

80
Q

system stack: software

A

problem, algorithm, program

81
Q

system stack: hardware

A

microarchitecture, circuits, transistors

82
Q

Moore’s Law

A

transistor counts double every 18-24 months on a single chip (means the performance will double)

83
Q

PC (program counter)

A

contains the address of the next instruction to execute; called “%eip” (IA32) or “%rip” (x86-64)

84
Q

register file

A

collection of registers; used to store heavily used program data

85
Q

condition codes

A

store status information about most recent arithmetic operation; used for conditional branching

86
Q

memory

A

byte addressable array; code, user data, some OS data; includes stack used to support procedures

87
Q

three basic operations of machine instructions

A
  1. arithmetic and logic operation (ALU)
  2. memory operation (AKA data movement)
  3. control-flow operation
88
Q

x86 is a (CISC/RISC) type

A

CISC

89
Q

CISC

A

Complex Instruction Set Computers; large number of instructions, varying instruction length, various addressing formats, complex compiler and hardware, compact code size

90
Q

RISC

A

Reduced Instruction Set Computers; smaller number of instructions, fixed instruction length, only a few addressing formats, simpler compiler and hardware, larger code size

91
Q

assembly data types

A

integer data (including memory address), floating point data; no aggregate types such as arrays or structures, just continuously allocated bytes in memory

92
Q

assembly operations

A

perform arithmetic/logical function on register or memory data, transfer data b/w memory and register, transfer control

93
Q

disassembler

A

useful tool for examining object code; analyses bit pattern of series of instructions, produces approximate rendition of assembly code, can be run on either a.out (complete executable) or .o file

94
Q

x86-64 Integer registers

A

supposed to contain integer value or memory address; can reference low-order 4 bytes; controlled by compiler; 16 registers

95
Q

IA32 integer registers

A

8 integer registers (first 6 - general purpose, %esp: stack pointer, %ebp: base pointer); can reference low-order 1 byte, 2 bytes, and 4 bytes; 16-bit registers with backwards compatibility

96
Q

operand types

A

immediate, register, memory

97
Q

immediate operand type

A

constant integer data; like C constant, but prefixed w/ ‘$’; encoded with 1, 2, or 4 bytes

98
Q

register operand type

A

one of 16 integer registers; %rsp reserved for special use; others have special uses for particular instructions

99
Q

memory operand type

A

8 consecutive bytes of memory at address given by register; various other “address modes”

100
Q

simple memory addressing modes

A

Normal: (R) Mem[Reg[R]]
Diplacement: D(R) Mem[Reg[R]+[D]]

101
Q

complete memory addressing modes

A

most general form: D(Rb, Ri, S)
Mem[Reg[Rb] + S*Reg[Ri]+D]
where D = constant “displacement”, Rb = base register, Ri = index register, and S = scale

102
Q

special memory address cases

A

(Rb, Ri) > Mem[Reg[Rb]+Reg[Ri]]
D(Rb, Ri) > Mem[Reg[Rb]+Reg[Ri]+D]
(Rb, Ri, S) > Mem[Reg[Rb]+S*Reg[Ri]]

103
Q

ALU two operand instructions (Src, Dest)

A

addq (+), subq (-), imulq (*), salq (<>), shrq (»), xorq (^), andq (&), orq (|)

104
Q

ALU one operand instructions (Dest)

A

incq (Dest+1), decq (Dest-1), negq (-Dest), notq (~Dest)

105
Q

leaq Src, Dest

A

pure ALU instruction that simply computes memory addresses (in contrast to movq, which accesses memory); Src is address mode expression, set Dst to address denoted by expression; useful for computing addresses without a memory reference and computing arithmetic instructions fo the form x+k*y

106
Q

control flow instructions: processor state

A

info about currently executing program:

temporary data, location of runtime stack, location of current code control point, status of recent tests

107
Q

condition codes for single bit registers

A

CF - Carry Flag (for unsigned), ZF - Zero Flag, SF - Sign Flag (for unsigned), OF - Overflow Flag (for signed)

108
Q

implicitly set condition codes by arithmetic operations

A

e.g. addl Src, Dest //t = a+b
CF set if carry out most significant bit (used for unsigned comparisons)
ZF set if t==0
SF set if t<0 (as signed)
OF set if two’s complement (signed overflow): (a>0 && b<0 && (a-b)<0) || (a<0 && b>0 && (a-b) > 0)

109
Q

condition codes explicit setting by Test instruction

A

testl/testq Src2, Src1
testl b,a like computing a&b without setting destination
sets condition codes based on value of Src1 & Src2
useful to have one of the operands be a mask
ZF set when a&b == 0
SF set when a&b < 0

110
Q

C data type char size

A

1 byte

111
Q

C data type short size

A

2 bytes

112
Q

C data type int size

A

4 bytes

113
Q

C data type long size

A

4 bytes

114
Q

C data type long long size

A

8 bytes

115
Q

C data type float size

A

4 bytes

116
Q

C data type double

A

8 bytes

117
Q

C data type long double size

A

8 bytes

118
Q

C data type pointer size

A

4 bytes

119
Q

condition codes explicit setting by Compare instruction

A

cmpl/cmpq Src2, Src1
cmpl b,a like computing a-b (subtraction) without setting destination
CF set if carry out from most significant big (for unsigned)
ZF set if a==b
SF set if (a-b)<0 (as unsigned)
OF set if two’s complement (signed) overflow

120
Q

SetX instructions

A

set a single byte based on combo of condition codes

one of 8 addressable byte registers; does not alter remaining 3 bytes; typically use movzbl to finish job

121
Q

jX instructions

A

jump to a different part of the code depending on condition codes

122
Q

jump target

A

in assembly code - symbolic labels

in machine binary - PC relative, absolute

123
Q

difference between while, do-while, and for loops

A

do while will run at least once
while checks condition first
for loop initializes, tests, and updates in condition

124
Q

mechanisms in procedures

A

passing control (to beginning of procedure code or back to return point), passing data (procedure arguments, return value), memory management (allocate during procedure execution, de-allocate upon return)

all implemented with machine instructions; x86-64 implementation of a procedure only uses those mechanisms required

125
Q

x86-64 stack

A

region of memory managed with stack discipline (FILO), grows toward lower addresses, register %rsp contains the address of the top of the stack (lowest address)

126
Q

x86-64 stack: push

A

pushq Src (Dest implicit > top of stack)

  • fetch (read) operant at Src
  • decrement %rsp by 8
  • write operand at address given by %rsp
127
Q

x86-64 stack: pop

A

popq Dest

  • read value at address given by %rsp
  • increment %rsp by 8
  • store value at Dest (must be register)

Fall 2017 (24 decks)

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