Computer organisation and architecture

Question 1

Addressable memory

Answer 1

The concept of storing data and instructions in a memory with discrete, unique addresses.

Question 2

Address bus

Answer 2

A bus that carries the memory location address of the register the data is being carried to or from.

Question 3

Control bus

Answer 3

A part of the CPU that controls and manages the executions of instructions. It sends control signals to coordinate execution and controls Fetch-Decode-Execute cycles and buses.

Question 4

Data bus

Answer 4

A bi-directional bus for carrying data and instructions between the processor and memory.

Question 5

Harvard architecture

Answer 5

A computer architecture that stores data and instructions in separate memories to allow the next instruction to be read while data is currently being read or written.

Question 6

I/O controllers

Answer 6

An interface that allows the processor to communicate with Input/Output devices connected to the computer.

Question 7

Main memory

Answer 7

A data store for instructions for the processor that can be directly addressed by the processor.

Question 8

Processors

Answer 8

A complex chip of transistors capable of executing programs, computer data to outputs, and supervising the operation of a computer system.

Question 9

Von Neumann architecture

Answer 9

A computer architecture where a single control unit manages program control via a linear sequence of fetch-decode-execute cycles. Data and instructions are held in the same memory.

Question 10

Stored program concept

Answer 10

Machine code instructions stored in main memory are fetched and executed serially by a processor that performs arithmetic and logical operations.

Question 11

Arithmetic and logic unit (ALU)

Answer 11

A part of the processor that performs arithmetic calculations and logical operations on data for the computer programs.

Question 12

Clock

Answer 12

A timing device connected to the processor that periodically generates a signal to synchronise fetch, decode, execute cycle runs and other components of the computer.

Question 13

Control unit

Answer 13

A part of the processor that controls and manages the execution and controls Fetch-Decode-Execute cycles and buses.

Question 14

Current instruction register

Answer 14

A dedicated register that stores the address of the instruction that is being executed in the processor.

Question 15

Dedicated register

Answer 15

A register reserved for a specific purpose or role essential to the running go the processor.

Question 16

General purpose registers

Answer 16

Special memory cells in the processor that can be accessed quickly. They temporarily store data and control information.

Question 17

Memory address register

Answer 17

A special register that stores the memory address of the next instruction to load or data to use.

Question 18

Memory buffer register

Answer 18

A special register that temporarily stores data to be read from or written to the computer’s memory.

Question 19

Program counter

Answer 19

A dedicated register that stores the address of the next instruction to execute.

Question 20

Status register

Answer 20

A dedicated register containing information about the intermediate states or outcomes of various processes in the processor.

Question 21

Fetch-decode-execute cycles

Answer 21

The process of fetching from memory (supplying the address and retrieving the instruction from memory), decoding (interpreting the instruction and then reading and retrieving the required data from their addresses) and executing the instruction (CPU carries out the required actions).

Question 22

Instruction set

Answer 22

A set of sequenced operations in machine code that can be recognised by a particular processor as the execution of a command.

Question 23

Opcode

Answer 23

The part of an instruction that explains what action the instruction performs.

Question 24

Operand

Answer 24

The part of an instruction with a value, memory address or register that the instruction will act on during its execution.

Question 25

Direct addressing

Answer 25

A form of addressing an instruction such that the operand is the address of the required datum (singular of data).

Question 26

Immediate addressing

Answer 26

A form of addressing an instruction such that the operand is the required datum (singular of data).

Question 27

Add

Answer 27

A machine code instruction that adds a given value to the value in a register, and stores the sum in the specified destination memory address.

Question 28

Branch

Answer 28

A set of machine code instructions that allow you to move to another part of the program either always (unconditional branching) or if a particular condition is met (conditional branching).

Question 29

Halt

Answer 29

A machine code instruction that stops the execution of the program.

Question 30

Load

Answer 30

A machine code instruction that loads the value stored in the memory address specified in the instruction.

Question 31

Logical bitwise operators

Answer 31

A set of machine code instructions designed to perform a specified logical operation (OR, AND, NOT etc.) on two or more values, string the result in the specified destination memory address.

Question 32

Logical shift

Answer 32

A machine code instruction that can shift the value stored in a given register by a number of bits (also given in the instruction) left or right, and stores the result in the specified destination memory address.

Question 33

Store

Answer 33

A machine code instruction that transfers the value from a specified register to a designated memory address.

Question 34

Subtract

Answer 34

A machine code instruction that subtracts a given value from the value in a register, and stores the difference in the specified destination memory address.

Question 35

Interrupt

Answer 35

A signal sent by a program to request the processor for attention from the current task(s).

Question 36

Interrupt service routine (ISR)

Answer 36

A block of code used by the processor to approximately handle and deal with an interrupt if it chooses to accept it.

Question 37

Input devices

Answer 37

Peripheral devices that allow the user to communicate and to pass readable data into a computer, decode it and send it to the CPU.

Question 38

Output devices

Answer 38

Peripheral devices that take convert signals from a computer into a human-readable form.

Question 39

Hard disk

Answer 39

A secondary storage device consisting of circular magnetic discs. Data is stored magnetically in concentric circles on each disc, and is accessed by moving parts.

Question 40

Optical disk

Answer 40

A secondary storage device consisting of a single disc that stores data as pits and lands on the disc’s surface, which can be read using a laser.

Question 41

Solid state disk

Answer 41

A secondary storage device consisting of NAND flash memory and a controller that stores data electronically with no moving parts.