Computer Architecture

Question 1

Arithmetic Logic Operator(ALU)

Answer 1

• The part of a computer processor (CPU) that carries out arithmetic (addition/subtraction)
• and logic operations (AND, OR, NOT)
• On the operands in computer instruction

Question 2

Control Unit(CU)

Answer 2

• Fetches each instruction in turn and manages their execution
• Handles all processor control signals.
• It directs all input and output flow, fetches code for instructions and directs them

Question 3

Bus

Answer 3

• To connect the internal components of CPU
• Pathway for transmitting data and instructions
• Examples: Address Bus, Control Bus, Data Bus

Question 4

Address Bus

Answer 4

• Carries the address of the next item to be fetched

- Data travels in only one direction (unidirectional)

Question 5

Control Bus

Answer 5

• Carries signals and actions of CPU

- can be unidirectional or bidirectional

Question 6

Data Bus

Answer 6

• Carries data that is being processed

- data can travel in both directions (bidirectional)

Question 7

Accumulator

Answer 7

-During calculations, the data is temporarily held in a register called the Accumulator (ACC)

Question 8

Register

Answer 8

-Holds data or instructions temporarily when they are being processed

Question 9

Immediate Store Access (IAS)

Answer 9

• The central processing unit (CPU) fetches the data instructions needed
• and stores them in the Immediate Access Store (IAS) to wait to be processed

Question 10

Explanation of Von Neuman’s Fetch, Decode and Execute Cycle

Answer 10

1. Central Processing Unit (CPU) fetches the data and instructions needed and stores them in the Immediate Access Store (IAS) to wait to be processed.
2. The Program Counter (PC) holds the address of the next instruction.
3. This address is sent to the Memory Address Register (MAR) through the Address Bus
4. The data from this address is sent to the Memory Data Register (MDR) which holds the current instruction in use, from address in MAR
5. Instruction is transferred using Data bus
6. From there, it’s copied onto Current Instruction Register (CIR)
7. Program Counter (PC) is incremented to point to the next instruction that’s to be fetched
8. Address of the instruction is paced in the Memory Address Register (MAR)
9. The instruction can then be decoded and executed thus completing the fetch, decode, execute cycle