Chapter 9: Chipset Flashcards
System and chip designers generally use a key metric known as
Cycles Per Instruction (CPI)
CPIs are used to measure the number of what?
Processor Clocks that system uses to execute an instruction.
While the number of instructions to execute an operating is held constant, the number of what decreases?
The number of cycles.
Chipset defines operation of what types of devices?
PCI, SATA, USB, RAID, and more.
The chipset optimizes operation of what?
The CPU
Controls data flow between what components?
Processor, memory, PCI devices, and system bus.
All access to the CPU is controlled through the?
Chipset
To minimize performance bottlenecks, you want to match the right chipset with the right?
CPU
Decreasing the cycles required to process an operation, combined with what increases system performance?
Higher clock rate
Servers have what type of workload?
Random
What depends on the chipset to quickly transfer information from main memory?
The CPU
The two multi-processor architectures available in System X servers are?
SMP and NUMA
SMP stands for?
Symmetric Multiprocessing
When using SMP, what does each CPU “see”?
The same hardware resources
What is one disadvantage to SMP?
Limited scalability
NUMA stands for?
Non-uniform memory access
True / False: NUMA is only for memory?
False, NUMA can also access I/O resources
In NUMA, every processor or group of processors has a certain amount of what?
Memory Local to It
The primary difference between NUMA and SMP is?
NUMA has multiple memory subsystems.
What is SRAT?
Static Resource Allocation Table
AMDs version of SRAT is?
SUMO - Sufficiently Uniform Memory Organization
What is a complicating factor for the design of any SMP system?
The need to keep all CPU and cache data coherent.
A protocol called ____ is employed on all Intel multi-processor configurations to ensure that each CPU is guaranteed to get the most recent copy of data even when other CPUs are currently using that data.
MESI
MESI stands for?
Modified, Exclusive, Shared, Invalid.
To support the MESI protocol, regular communication must occur between every ___ whenever data is loaded into a cache.
CPU
Snoop Cycles occur when?
Every memory read or write operation
If the operation is a SMP write request, the CPU that possesses the unmodified data must mark its data as?
Invalid
If the operation is a SMP read request, the CPU that possesses the unmodified data must mark its data as?
Shared
AMD uses a slightly different version of MESI called?
MOESI
The primary difference between MESI and MOESI is?
The owner statis flag
The larger the L2 cache, the greater the probability that _____ requests will hit data in another processor cache.
snoop
The Intel front-side bus protocol is limited to how many processor sockets.
Four
What is UEFI?
Unified Extensible Firmware Interface
What replaced BIOS after nearly 20 years?
UEFI
In opteron processors, the processor and ______ _________ logic are integrated into the same piece of silicon.
Memory Controller
When four processors are placed at the edges of a square, what type of remote access occurs?
two-hop remote memory access
