Chapter 8: PCI bus subsystems Flashcards
Name each coloured arrow for the PCI-X Keying.
- 64-bit slot and connector
- 5V Slot
- 3.3V slot
A single PCI Express serial link is a ____-_______connection
Dual-Simplex
PCI adapters that have the ability to gain direct access to system memory are called?
Bus Master Devices
The two pair connection in PCI E is called
A Lane
PCI-X operates at __ MHz and __MHz.
66 and 133.
When supporting previous PCI devices, it is important to note that the clock must scale to a frequency that is acceptable to what?
Lowest speed device on the bus.
PCI Express uses a ______ (serial | parallel) interface
Serial
Delayed transactions in conventional PCI are replaced by what in PCI-X?
Split Transactions
PCI-X has raised the maximum transfer rate in burst mode from 276 MBps to?
4.2GBps
PCI E uses two pairs of wires. What are they used for?
One pair for transmit and oce for Receive.
The downside to multi-drop parallel bus is that transactions must include a __________ phase.
Turnaround
A basic data transfer operation on the PCI bus is called a PCI
Transaction
The generic name for any PCI device is the?
Agent
PCI uses a multi-drop parallel bus that is called?
multiplexed address and data bus
The benefit of adopting the PCI-X standard is?
The Increased in supported throughputs.
Responding PCI Agents are called
Targets
All PCI operations are references from
Memory
PCI Stands for
Peripheral Component Interconnect
PCI-X V2.2 enables a data throughput of over?
4 GBps at 533MHz
PCI agents that initiate a bus transfer are called
Initiators
The attribute phase takes how many clock cycle(s)?
One
The standard PCI bus uses a __ MHz or __ MHz clock
33 or 66
PCI-X cards are not designed usually to run at?
100MHz
Define PCI
Peripheral Component Interface
Define PCI-X
PCI eXtended
What two PCI components should be matched for optimal performance
PCI card and PCI bus
What kind of bus is the PCI bus
Synchronous Bus
What is the MHz of the clock edge
33MHz or 66MHz
What are the two possible PCI bus widths
32 or 64 bits
PCI uses what type of address bus
Multiplexed address and data bus
What phase causes slower data transfers
Turnaround phase
What is the theoretical maximum throughput of the standard PCI bus
132MB/s to 528MB/s
What is the actual throughput of the standard PCI bus
75% of theoretical (100MB/s to 398Mb/s)
What is the purpose of the turnaround phase
Switch from address mode to data mode
A PCI device is called
PCI agent
A PCI operation is called
PCI transaction
The agent that initiates a transfer is called the
Initiator
The agent that responds to a transfer is called the
Target
PCI uses how many CPU cycles
None (use the front side bus)
PCI-X is compatible with traditional PCI on a hardware level (T/F)
True
The PCI-X bus is scaled to which PCI device
The slowest
List the common PCI-X bus speeds
66MHz 133MHz 133MHz DDR and 133MHz QDR (533MHz possible)
Define QDR
Quad Data Rate
Describe how QDR works
Separate inputs and outputs that operate at double data rate
Why would you use DDR and QDR
To increase performance without increasing clock speed because increasing clock speed uses more energy
How many bits are transferred per clock on QDR
2
At what points are data transferred in QDR
Rising and falling edges two points in between
Define QDR-SPB-SRAM
Quad Data Rate Synchronous Pipeline Burst Static Random Access Memory
PCI-X 2.0 supports QDR at what speed
PCI-X 522MHz
What is the maximum bandwidth of PCI-X 533
4.26GB/s at 64 bits
What is the maximum bandwidth of PCI-X 133
1.06GB/s
What are the three PCI-X performance factors
- Attributes phase 2. Split transaction 3. Allowable disconnect boundary
Describe the attributes phase of PCI-X
One extra clock cycle provides more information about the transaction for buffer management
Describe the split transactions of PCI-X
Replaces delayed transactions and frees bus for communications
Describe the allowable disconnect boundary of PCI-X
Prevents a single process from monopolizing PCI bus with large transfers
The PCI-X sequence information identifies what
Total number of bytes remaining to be read or written
What happens when a transaction is disconnected
New transaction that continues the sequence includes update byte count
Each transaction includes the identity of what
The initiator (bus number device number function number)
What does the relaxed order structure allow
PCI-PCI bridges to rearrange the transactions on the bus
PCI Express uses what type of interface
Serial
PCI Express has how many wire pairs
Two (dual simplex)
What are the PCI pairs used for
One transmit pair one receive pair
What is a PCI-Express lane
A two wire pair
What is a gigatransfer
Raw data rate (bits per second that a bus can move)
Encoding overhead takes what percent of the GT/second speed
20%
8GT/sec translates to what
6.4GT/sec of useful data (6.4GB/sec or 800Mb/sec)
PCI-E is compatible with traditional PCI on a hardware level (T/F)
False
PCI-E is compatible with traditional PCI on a software level (T/F)
True
PCI-to-PCI briges allow for what
Multiple speeds of PCI buses at once
The PCI-to-PCI bridge interface is located where
In the memory controller
What part of the PCI-E connectors does not need to be managed the same was as PCI or PCI-X
The bandwidth
What kind of connection is PCI-Express
Point-to-Point
Point-to-point connection of PCI-E is a what
Switched fabric for high performance
The combined speed of PCI-X edge connectors cannot exceed what
Allocated bandwidth between memory controller and PCI bridge
