Chapter 36 Flashcards
how a logical address convert into physical address
There are several ways like
- Simple indexing
- Multi-level indexing
- Hashing
- TLB (translation lookaside buffer)
What is valid and invalid bit in paging
One additional bit is generally attached to each entry in the page table: a valid–invalid bit. When this bit is set to valid, the associated page is in the process’s logical address space and is thus a legal (or valid) page. When the bit is set to invalid, the page is not in the process’s logical address space.
Does segmentation could also have additional bits
Yes read write & execute bits
How 2 types of protection can be implemented on segmentation level
- Associate valid/invalid bit with each segment table entry to indicate if the referenced segment is part of the process address space or not.
- Read, write and execute bits to define legal operations on a segment with 0/1 values.
Can we do paging with external segmentation
Yes. Then each will have page table. This process is known as paged segmentation. The reason for paged segmentation is that segmentation sizes are increasing.
What is level of page segmentation in intel
2 level
What is TLB reach
How much memory TLB can cover
What kind of 2 segments supported by Intel CPU
- Local segments (accessible only for 1 process)
2. Global segments (can be shared between different processes)
What are 2 modes in Intel CPU
- Real mode
2. Protected mode