Chapter 33 Flashcards
1
Q
Page table entry have each frame number
A
Yes
2
Q
What are 2 methods to implement page table
A
- The CPU should be designed in a way that page table should be in CPU
- Page table should be in main memory
3
Q
What is effective memory access time
A
The time taken to convert logical address into physical address and access memory is called effective memory time
4
Q
What is PTBR
A
Page table base register
5
Q
What is TLB
A
A translation lookaside buffer (TLB) is a memory cache that stores recent translations of virtual memory to physical addresses for faster retrieval. When a virtual memory address is referenced by a program, the search starts in the CPU. First, instruction caches are checked.
6
Q
What is hit ratio
A
The percentage of time you have a hit for TLB is called hit ratio
7
Q
What is miss ratio
A
The percentage of time you do not find something in cache is called miss ratio
