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A OCR Computer Science A level > Chapter 2 - Processor performance > Flashcards

Chapter 2 - Processor performance Flashcards

1
Q

What are the 3 main factors which affect processor performance?

3 Marks

A

» Clock speed
» Number of cores
» Amount/type of cache memory

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2
Q

What is the definition of clock speed?

1 Mark

A

» It is the number of FDE cycles the CPU can process per second and it is measured in hertz (Hz)

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3
Q

Why can the CPU not perform operations faster than the clock cycle?

A

» Each CPU operation starts as the clock changes from 0 to 1, therefore cannot perform operations faster than the clock cycle

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4
Q

What is clock speed measured in ?

1 Mark

A

» Gighertz

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5
Q

What will be the consequence for a greater clock speed?

3 Marks

A

» More instructions will be executed
» As more there is a greater rate of FDE cycles happening per second
» So the program takes less time to run

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6
Q

What is the key feature of the Von Neumann architecture?

To do with the instructions

A

» Instructions are fetched and executed one a time in a serial manner

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7
Q

What does a Dual - core processor have?

A

» 2 Processor linked together in the same integrated circuit

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8
Q

» What is the benefit of having a dual core processor?

A

» Each core is able to process a different instruction at the same time with its own F-D-E cycle

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9
Q

What is one key fact about cache?

A

» It is much faster than RAM

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10
Q

What happens when the cache fills up?

1 Mark

A

» Unused instructions or data still being held are replaced with more recent ones

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11
Q

How many types of cache level are there?

1 Mark

A

» L1
» L2
» L3

3

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12
Q

What is the fastest type of cache?

A

» Level 1 cache,
» But it is very small, usually between 2-64 Kb

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13
Q

What is Level 2 cache?

A

» Slower than level 1,
» But has a bigger size, approximately between 256Kb-2MB

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14
Q

What is the final cache level?

A

» Level 3

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15
Q

Why do some processors use pipelining?

2 Marks

A

» It is a technique used by some processors to improve performance
» Reduces latency as CPU is not idle while waiting for the next instruction

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16
Q

What happens without pipelining?

1 Mark - To do with the FDE cycle

A

» The steps in the FDE cycle takes place one after the other, while one instruction is being fetched, the ALU is idle

17
Q

What is the definition of pipelining?

3 Marks

A

» Allows the next instruction to be fetched at the same time as the previous instruction is being decoded, and the one before that is being executed
» It is the concurrent processing of multiple instructions
» Increases speed of execution

18
Q

What are the 2 types of processor pipelining?

1 mark

A

» Instruction pipelinining
» Arithmetic pipelining

19
Q

What is the instruction pipeline?

1 Mark

A

» Consists of the stages which an instruction is moved through the processor
» Such as it being fetched, buffered and then executed

20
Q

What is the arithmetic pipelining?

1 Mark

A

» Represents the parts of an arithmetic operation that can be broken down and overlapped as they perform

21
Q

What does each word, or group of bytes in memory have?

1 Mark

A

» Its own specific address

22
Q

How does the processor read a word of data from memory?

A

» Puts the address of the desired word on the address bus

23
Q

What does the wdith of the address bus determine?

1 Mark - to do with memory

A

» The maximum possible memory capacity of the system

24
Q

What happens if the address bus consists of only 8 lines?

1 Mark - Talk about maximum address

A

» Maximum address it can transmit is 255
» Maximum memory capacity is 256, including the address 0

25
Q

What is the purpose of the data bus?

A

» Transmits the data held in a word of memory, between processor components and memory

26
Q

What happens if the bus is only 17 bits wide?

A

» A word cannot hold an integer greater than 2^16 - 1, or more than characters

27
Q

What is the affect of a wider data bus?

1 Mark

A

» It can transmit larger values, or more characters at a time, or allow more bits per instruction

28
Q

How will the opcode be expressed in assembly language?

A

» Using a mnemonic

29
Q

What are some examples of how opcode will he expressed in main memory?

4 Marks

A

» ADD - Additions
» SUB - Subtraction
» LDA - Load into accumulator
» BRA - Branched into the accumulator

30
Q

How many bits is the opcode in a 16bit word?

A

» Only 6 bits

31
Q

How many bits in the operand for a 16bit word?

32
Q

How many bits for the addressing mode for a 16bit word?

33
Q

What can cause the pipeline to be flushed?

2 Marks

A

» iterations can cause the value in the program counter to change
» As the wrong instruction can be fetched/decoded which causes the pipeline to flush

34
Q

What is a core?

A

» A distinct processing unit within the CPU

A OCR Computer Science A level (75 decks)

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