BUS II Flashcards
ELEMENTS OF BUS DESIGN:BUS TYPES
What are the types of bus lines?
Bus lines can be separated into two generic types: dedicated and multiplexed.
• A dedicated bus line is permanently assigned either to one function or to a physical subset of computer components.
ELEMENTS OF BUS DESIGN:BUS TYPES
What is physical dedication and what are its advantages and disadvantages?
- Physical dedication refers to the use of multiple buses, each of which connects only a subset of modules.
- The potential advantage of physical dedication is high throughput, because there is less bus contention.
- A disadvantage is the increased size and cost of the system.
ELEMENTS OF BUS DESIGN:BUS TYPES
What is the advantage and disadvantage of multiplexing buses?
• The advantage of time multiplexing is the use of fewer lines, which saves space and, usually, cost. The disadvantage is
that more complex circuitry is needed within each module
ELEMENTS OF BUS DESIGN:METHOD OF ARBITRATION
Describe the different methods of arbitration
- The various methods can be roughly classified as being either centralized or distributed.
• In a centralized scheme, a single hardware device, referred to as a bus controller or arbiter, is responsible for allocating time on the bus.
• In a distributed scheme, there is no central controller.
• Rather, each module contains access control logic and the modules act together to share the bus.
ELEMENTS OF BUS DESIGN:METHOD OF ARBITRATION
What is the purpose of arbitration?
- With both methods of arbitration, the purpose is to designate either the processor or an I/O module, as master.
- The master may then initiate a data transfer (e.g., read or write) with some other device, which acts as slave for this particular exchange.
ELEMENTS OF BUS DESIGN:TIMING
What are the different types of timing
- Buses use either synchronous timing or asynchronous timing.
• With synchronous timing, the occurrence of events on the bus is determined by a clock.
• A single 1–0 transmission is referred to as a clock cycle or bus cycle and defines a time slot.
• Asynchronous timing, the occurrence of one event on a bus follows and depends on the occurrence of a previous event.
ELEMENTS OF BUS DESIGN:BUS WIDTH Describe the impact of the width of the bus width
- The width of the data bus has an impact on system performance:
- The wider the data bus, the greater the number of bits transferred at one time.
- The width of the address bus has an impact on system capacity:
- the wider the address bus, the greater the range of locations that can be referenced.
ELEMENTS OF BUS DESIGN: DATA TRANSFER TYPE
Describe and illustrate how the bus supports different data transfer types.
A bus supports various data transfer types.
• In the case of a multiplexed address/data bus, the bus is first used for specifying the address and then for transferring the data.
• For a read operation, there is typically a wait while the data are being fetched from the slave to be put on the bus.
• For either a read or a write, there may also be a delay if it is necessary to go through arbitration to gain control of the bus for the remainder of the operation.
*See notes for figure
How many mandatory signal lines for PCI exist?
49
Describe the 9 functional groups of the mandatory PCI signal lines
• System pins: Include the clock and reset pins.
• Address and data pins: Include 32 lines that are time multiplexed for addresses and data. The other lines in this group are used to interpret and validate the signal lines that carry the addresses and data.
• Interface control pins: Control the timing of transactions and provide coordination
among initiators and targets.
• Arbitration pins: Unlike the other PCI signal lines, these are not shared lines. Rather, each PCI master has its own pair of arbitration lines that connect it directly to the PCI bus arbiter.
• Error reporting pins: Used to report parity and other errors. In addition, the PCI specification defines 51 optional signal lines, divided into the following functional groups:
• Interrupt pins: These are provided for PCI devices that must generate requests for service. As with the arbitration pins, these are not shared lines. Rather, each PCI device has its own interrupt line or lines to an interrupt controller.
• Cache support pins: These pins are needed to support a memory on PCI that can be cached in the processor or another device.
• 64-bit bus extension pins: Include 32 lines that are time multiplexed for ad dresses and data and that are combined with the mandatory address/data lines to form a 64-bit address/data bus.
• JTAG/boundary scan pins: These signal lines support testing procedures.
How do bus activities occur?
- Bus activity occurs in the form of transactions between an initiator, or master, and a target.
- When a bus master acquires control of the bus, it determines the type of transaction that will occur next.
List 12 PCI commands
- Interrupt Acknowledge
- Special Cycle
- I/O Read
- I/O Write
- Memory Read
- Memory Read Line
- Memory Read Multiple
- Memory Write
- Memory Write and Invalidate
- Configuration Read
- Configuration Write
- Dual address Cycle
Advantages of High-Performance Bus Architecture
Brings high-demand devices into closer integration with the processor
It is independent of the processor. So changes in processor architecture also do not affect the high-speed bus
Efficiency- permit several devices to work simultaneously, reducing time spent waiting and improving the computer’s speed.
Expansion- Having multiple buses available gives you more choices for connecting devices to your computer, as hardware makers may offer the same component for more than one bus type.
What are the common elements used in BUS design?
Bus Types
Bus lines can be reported into two generic types are dedicated and multiplexed.
Method of Arbitration
In all but the simplest systems, more than one module can require control of the bus. Therefore only one unit at a time can strongly transfer over the bus, some method of arbitration is required. Various methods can be classified as centralized or distributed.
Timing
Timing defines how events are integrated on the bus. With synchronous timing, the circumstances of events on the bus are persistent by a clock.
Bus Width
The width of the data has an impact on system execution. The wider the data bus, the higher the number of bits moved at one time.
Bus Width
The width of the data has an impact on system execution. The wider the data bus, the higher the number of bits moved at one time.
