BUS Flashcards
What is an interconnection structure?
The collection of paths connecting the various modules in a computer
What are the types of transfers in the computer?
- Memory to CPU
- CPU to Memory
- I/O to CPU
- CPU to I/O
- I/O to or from Memory (DMA)
What is a bus?
• A bus is a communication pathway connecting two or more devices. A key characteristic of a bus is that it is a shared transmission medium.
Describe data transmission in a bus
- Multiple devices connect to the bus, and a signal transmitted by any one device is available for reception by all other devices attached to the bus.
- If two devices transmit during the same time period, their signals will overlap and become garbled.
- Thus, only one device at a time can successfully transmit.
- Typically, a bus consists of multiple communication pathways, or lines.
- Each line is capable of transmitting signals representing binary 1 and binary 0
What is a system bus
A bus that connects major computer components (processor, memory, I/O)
Draw a representation of a bus
*see notes for picture
Describe the classification of the functional groups of the lines on a bus
There are data, address, and control lines.
• In addition, there may be power distribution lines that supply power to the attached modules.
Describe the data lines
- The data lines provide a path for moving data among system modules.
- These lines, collectively, are called the data bus.
Describe the address lines
- The address lines are used to designate the source or destination of the data on the data bus.
- For example, on an 8-bit address bus, address 01111111 and below might reference locations in a memory module (module 0) with 128 words of memory, and address 10000000 and above refer to devices attached to an I/O module (module 1).
Describe the control lines
- The control lines are used to control the access to and the use of the data and address lines.
- Control signals transmit both command and timing information among system modules
- Timing signals indicate the validity of data and address information. Command signals specify operations to be performed.
List typical types of control lines
- Memory write: Causes data on the bus to be written into the addressed location
- Memory read: Causes data from the addressed location to be placed on the bus
- I/O write: Causes data on the bus to be output to the addressed I/O port
- I/O read: Causes data from the addressed I/O port to be placed on the bus
- Transfer ACK: Indicates that data have been accepted from or placed on the bus
- Bus request: Indicates that a module needs to gain control of the bus
- Bus grant: Indicates that a requesting module has been granted control of the bus
- Interrupt request: Indicates that an interrupt is pending
- Interrupt ACK: Acknowledges that the pending interrupt has been recognized
- Clock: Is used to synchronize operations
- Reset: Initializes all modules
Describe the operation of the bus
- If one module wishes to send data to another, it must do two things: (1) obtain the use of the bus, and (2) transfer data via the bus.
- If one module wishes to request data from another module, it must (1) obtain the use of the bus, and (2) transfer a request to the other module over the appropriate control and address lines.
- It must then wait for that second module to send the data.
Draw and describe the classical physical arrangement of a bus
• The bus consists of two vertical columns of conductors.
• Each of the major system components occupies one or more boards and plugs into the bus at these slots.
*see notes for picture
What is the difference between an on-chip and on-board bus
An on-chip bus may connect the processor and cache memory, whereas an on-board bus may connect the processor to main memory and other components.
Why is the classical arrangement of the bus convenient?
- A small computer system may be acquired and then expanded later (more memory, more I/O) by adding more boards.
- If a component on a board fails, that board can easily be removed and replaced.
Why does performance suffer when a great number of devices are connected to the bus?
- In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay.
- The bus may become a bottleneck as the aggregate data transfer demand approaches the capacity of the bus.
Draw and describe a typical traditional multiple-bus hierarchy
• There is a local bus that connects the processor to a cache memory and that may support one or more local devices The cache memory is connected to a system bus to which all of the main memory modules are attached.
*See notes for pic
What is the most efficient way to connect I/O controllers using buses
- It is possible to connect I/O controllers directly onto the system bus.
- A more efficient solution is to make use of one or more expansion buses for this purpose.
- This arrangement allows the system to support a wide variety of I/O devices and at the same time insulate memory-to-processor traffic from I/O traffic.
Describe and illustrate the mezzanine architecture
- This traditional bus architecture is reasonably efficient but begins to break down as higher and higher performance is seen in the I/O devices.
- In response to these growing demands, a common approach taken by industry is to build a high-speed bus that is closely integrated with the rest of the system, requiring only a bridge between the bus and the high-speed bus.
- Again, there is a local bus that connects the processor to a cache controller, which is in turn connected to a system bus that supports main memory.
- The cache controller is integrated into a bridge, or buffering device, that connects to the high-speed bus.
- This bus supports connections to high-speed LANs, video and graphics workstation controllers, SCSI and FireWireLower-speed devices are still supported off an expansion bus, with an interface buffering traffic between the expansion bus and the high-speed bus.
What is the advantage of the mezzanine architecture?
The advantage of this arrangement is that the high-speed bus brings high-demand devices into closer integration with the processor and at the same time is independent of the processor.
List the elements of bus design
Bus Types Method of arbitration Timing Bus Width Data transfer type
Describe the PCI
- The peripheral component interconnect (PCI) is a popular high-bandwidth, processor independent bus that can function as a peripheral bus.
- The current standard allows the use of up to 64 data lines at 66 MHz, for a raw transfer rate of 528 MByte/s, or 4.224 Gbps.
- It requires very few chips to implement and supports other buses attached to the PCI bus.
- PCI is designed to support a variety of microprocessor-based configurations, including both single- and multiple-processor systems.
- It makes use of synchronous timing and a centralized arbitration scheme
Describe and illustrate the typical use of a PCI in a single processor system
- The bridge acts as a data buffer so that the speed of the PCI bus may differ from that of the processor’s I/O capability.
- In a multiprocessor system (Figure b), one or more PCI configurations may be connected by bridges to the processor’s system bus.
- Again, the use of bridges keeps the PCI independent of the processor speed yet provides the ability to receive and deliver data rapidly.
*See notes for picture
