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1. Architecture & Networks (CSC 1022) > Architecture Textbook > Flashcards

Architecture Textbook Flashcards

1
Q

Personal Computer (PC)

A

Comp designed for use by individual, usually incorporating graphics display, keyboard + mouse.

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2
Q

Server

A

Comp used for running larger programs for multiple users, often simultaneously + typically accessed via network.

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3
Q

Supercomputer

A

Class of comps with highest performance + cost, configured as servers + cost tens to hundreds of millions of dollars.

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4
Q

Embedded Computer

A

Comp inside another device used for running 1 predetermined app or collection of software. Often have lower tolerance for failure.

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5
Q

Personal Mobile Devices (PMDs)

A

Small wireless devices to connect to Internet. Rely on batteries for power + software installed by downloading apps. e.g. phones + tablets

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6
Q

Cloud Computing

A

Large collections of servers that provide services over Internet. Some providers rent dynamically varying nums of servers as utility.

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7
Q

Software as a Service (SaaS)

A

Delivers software + data as service over Internet, usually via thin program such as browser that runs on local client devices, instead of binary code that must be installed + runs wholly on that device. E.g. web search + social networking.

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8
Q

Moore’s Law

A

States that integrated circuit resources double every 18 - 24 months.

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9
Q

Abstraction

A

Useful for productive, simplified design. Allows us to characterise the design at diff levels of representation. Lower level details hidden to offer simpler model at higher levels.

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10
Q

Systems software

A

Software that provides commonly useful services e.g. operating systems, compilers, loaders + assemblers.

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11
Q

Operating System

A

Supervising program that manages resources of comp for benefit of programs that run on it. Handles basic input/output operations, allocates storage + memory + provides for protected comp sharing among multiple apps.

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12
Q

Compiler

A

Program that translates high level language statements into assembly language statements.

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13
Q

Binary Digit/Bit

A

One of 2 numbers in base 2 (0 or 1) that are components of information.

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14
Q

Instruction

A

Command that comp hardware understands + obeys.

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15
Q

Assembler

A

Program that translates symbolic version of instructions into binary version.

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16
Q

Assembly Language

A

Symbolic representation of machine instructions.

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17
Q

Machine Language

A

Binary representation of machine instructions.

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18
Q

High-level Programming Language

A

Portable language composed of words + algebraic notation that can be translated by compiler into assembly language. Allow languages to be designed according to intended use. Improves programmer productivity as concise. Programs also indep of comp they’re developed on. e.g. C++, Java, Visual Basic

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19
Q

Input Device

A

Mechanism through which comp is fed info e.g. keyboard

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20
Q

Output Device

A

Mechanism that conveys result of computation to user e.g. display or to another comp.

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21
Q

5 classic components of computer

A

Input, output, memory, datapath + control. Datapath + control may be combined + called processor.

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22
Q

Liquid Crystal Display (LCD)

A

Display tech using thin layer of liquid polymers to transmit/block light according to where charge applied.

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23
Q

Active Matrix Display

A

LCD using transistor to control light transmission at each pixel.

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24
Q

Pixel

A

Smallest individual picture element. Screens composed of thousands to millions of them organised in a matrix.

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25
Q

Bit Map

A

Matrix of bits of pixels. e.g. 1024 x 768. Frame buffer will store this and bit pattern per pixel read out to graphics display at refresh rate.

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26
Q

Integrated Circuit/Chip

A

Device combining dozens to millions of transistors.

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27
Q

Central Processor Unit (CPU)/Processor

A

Active part of comp, contains datapath + control. Adds nums, tests nums, signals I/O devices to activate etc.

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28
Q

Datapath

A

Component of processor that performs arithmetic operations.

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29
Q

Control

A

Component of processor that commands datapath, memory + I/O devices according to program instructions.

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30
Q

Memory

A

Storage area in which programs are kept when running + contains data needed by running programs.

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31
Q

Dynamic Random Access Memory (DRAM)

A

Memory built as integrated circuit, provides random access to any location. Access times are 50 nanoseconds + cost per GB in 2012 was 5 to 10 dollars.

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32
Q

Cache Memory

A

Small, fast memory that acts as buffer for slower, larger memory. (DRAM) Built using SRAM.

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33
Q

Static Random Access Memory (SRAM)

A

Memory built as integrated circuit, faster + less dense than DRAM.

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34
Q

Instruction Set Architecture/Architecture

A

Abstract interface between hardware + lowest level software that encompasses all info necessary to write machine language program that will run correctly, including instructions, registers, memory access, I/O etc. Allows designers to talk about functions independently from hardware that performs them.

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35
Q

Application Binary Interface (ABI)

A

User portion of instruction set plus OS interfaces used by application programmers. Defines standard for binary portability across comps.

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36
Q

Implementation

A

Hardware that obeys architecture abstraction.

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37
Q

Volatile Memory

A

Storage, such as DRAM that retains data only if it receives power.

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38
Q

Nonvolatile Memory

A

Form of memory that retains data even in absence of power source + used to store programs between runs. e.g. DVD.

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39
Q

Main Memory/Primary Memory

A

Memory used to hold programs while running, typically DRAM.

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40
Q

Secondary Memory

A

Nonvolatile memory used to store programs + data between runs, typically flash in PMDs + magnetic disks in servers.

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41
Q

Magnetic Disk/Hard Disk

A

Form of nonvolatile secondary memory composed of rotating platters coated with magnetic recording material. As rotating mechanical devices, access times 5 to 20 milliseconds + cost 5 - 10 cents per GB in 2012.

42
Q

Flash Memory

A

Nonvolatile semi conductor memory. Cheaper + slower than DRAM, more expensive per bit + faster than magnetic disks. Access times 5 to 20 microseconds + cost 75 cents - 1 dollar per GB in 2012. Slower than DRAM but cheaper + nonvolatile Smaller, more rugged + more power efficient than magnetic disks. Wear out after 100k - 1 million writes though.

43
Q

Benefits of Networks

A

Communication (info exchanged at high speeds), resource sharing (can share I/O devices) + nonlocal access (don’t need to be near comp they’re using). Most pop type is ethernet, up to 1km long + 40GB/s, usually LAN.

44
Q

Local Area Network (LAN)

A

Network designed to carry data within geographically confined area, typically within single building. Interconnected with switches that provide routing services + security.

45
Q

Wide Area Network (WAN)

A

Network extended over hundreds of kilometers, can span a continent. Typically fibre optic + leased from telecommunications companies.

46
Q

Transistor

A

On/off switch controlled by electric signal. Add materials to silicon so areas can conduct/insulate under specific conditions (switch)

47
Q

Very large-scale integrated circuit (VLSI)

A

Device containing hundreds of thousands to millions of transistors.

48
Q

Silicon

A

Natural semiconductor element. Found in sand. Start of a chip. Can be chemically treated to add materials so it either is a good electricity conductor (copper), good electricity insulator (glass) or conduct/insulate under certain conditions (switch).

49
Q

Semiconductor

A

Substance that doesn’t conduct electricity well.

50
Q

Silicon Crystal Ingot

A

Rod composed of silicon crystal that is 8 - 12 inches diameter, 12 - 24 inches long.

51
Q

Wafer

A

Slice from silicon ingot no more than 0.1 inches thick, used to create chips.

52
Q

Defect

A

Microscopic flaw in wafer/patterning steps that can result in failure of die containing that defect. Best way to cope with this is place many indep. components on single wafer + dice into dies so can discard only flawed dies, rather than whole wafer. Increases yield.

53
Q

Die/Chip

A

Individual rectangular sections cut from wafer.

54
Q

Yield

A

Percentage of good dies from total num of dies on wafer.

55
Q

Bonding

A

Once you’ve found the good dies, they’re connected to I/O pins of a package using this process. They’re tested against before being sent to customers.

56
Q

Response Time/Execution Time

A

Total time required for comp to complete task, including disk accesses, memory accesses, I/O activities, OS overhead + CPU execution time etc. Equals num of instructions executed multiplied by average time per instruction.

57
Q

Throughput/Bandwidth

A

Measure of performance, num of tasks completed per unit time. Datacentre manager is interested in increasing this.

58
Q

Performance

A

Performance = 1/Execution time. To find how much faster A is than B: Performance A/Performance B = ExecutionTime B/ExecutionTime A = n.

59
Q

Wall clock time/response time/elapsed time

A

Total time to complete a task, including disk accesses, memory access, operating system overhead etc.

60
Q

CPU Execution time/CPU time

A

Time CPU spends computing for a specific task. CPU Execution Time for a Program = CPU clock cycle for a program x clock cycle time. CPU time = instruction time x CPI x clock cycle time.

61
Q

User CPU time

A

CPU time spent in program itself.

62
Q

System CPU time

A

CPU time spent in OS performing tasks on behalf of program.

63
Q

Clock Period

A

Length of each clock cycle e.g. 250 picoseconds, the clock rate (inverse of clock period) e.g. 4GHz.

64
Q

Clock Cycle/tick/clock tick/clock period/clock/cycle

A

Time for 1 clock period, usually of processor clock, which runs at constant rate. Clock rate + clock cycle time are inverses. CPU clock cycles = instructions for program x average clock cycles per instruction.

65
Q

Clock cycles per instruction (CPI)

A

Average num of clock cycles per instructions for program/program fragment.

66
Q

Instruction Count

A

Num of instructions executed by program.

67
Q

Instruction Mix

A

Measure of dynamic frequency of instructions across 1 or many programs. CPI varies by this.

68
Q

CMOS

A

Complementary Metal Oxide Semiconductor. Dominant tech for integrated circuits. Primary source of energy consumption is dynamic energy, consumed when transistors switch from 0 to 1 + vice versa. Dynamic energy depends on capacitive loading of each transistor + voltage applied. energy ∝ capacitive load x voltage^2. Single transistion is energy ∝ 1/2 x capacitive load x voltage^2. Power required per transistor is power ∝ 1/2 x capacitive load x voltage^2 x frequency switched.

69
Q

Frequency Switched

A

Function of clock rate.

70
Q

Capacitive load per transistor

A

Function of num of transistors connected to output (fanout) + tech which determines capacitance of wires + transistors.

71
Q

Lowering of voltage issues

A

Transistors too leaky. Improve power problem by attaching cooling devices, turning off parts of chip unused in given clock cycle.

72
Q

Core

A

A processor. Such microprocessors are called multicore microprocessors. So a quadcore microprocessor is a chip containing 4 processors/cores.

73
Q

Workload

A

Set of programs run on comp that is either actual collection of apps run by user or constructed from real programs to approximate such a mix. Typical workload specifies both programs + relative frequencies.

74
Q

Benchmark

A

Program selected for use in comparing comp performance.

75
Q

SPEC

A

System Performance Evaluation Cooperative. Creates standard set of benchmarks for modern comp systems. Also has a benchmark for measuring power, reporting server power consumption at diff workload levels.

76
Q

Amdahl’s Law

A

Rule stating that performance enhancement possible with given improvement is limited by amount that improved feature is used. Quantitative version of law of diminishing returns. Execution time after improvement = execution time affected by improvement/amount of improvement + execution time unaffected.

77
Q

MIPS

A

Million instructions per second. Measurement of program execution speed based on num of millions of instructions. Computed as instruction count/product of execution time x 10^6.n Specifies performance inversely to execution time, faster comps have higher MIPS rating. Doesn’t account for instruction capabilities, varies for programs on same comp + if new program executes more instructions but each instruction is faster, MIPS can vary from performance.

78
Q

Instruction Set

A

Vocab of commands understood by given architecture.

79
Q

Stored-Program Concept

A

Idea that instructions + data of many types can be stored in memory as numbers + so easy to change, leading to stored-program comp.

80
Q

Doubleword

A

Natural unit of access in comp, usually group of 64 bits. Corresponds to size of register in LEGv8 architecture.

81
Q

Word

A

Natural unit of access in comp, usually group of 32 bits.

82
Q

Data Transfer Instruction

A

A command that moves data between memory and registers.

83
Q

Address

A

A value used to delineate the location of a specific data element within a memory array.

84
Q

Load

A

The data transfer instruction that copies data from memory to a register. Format: Name of operation followed by register to be loaded, then register + constant used to access memory.

85
Q

Memory Address

A

The sum of the constant portion of the instruction and the contents of the second register. The real LEGv8 name for this instruction is LDUR, standing for load register. The U stands for unscaled.

86
Q

Base Register

A

Register added to form address.

87
Q

Offset

A

Constant in data transfer instruction.

88
Q

Store

A

Instruction complementary to load. Copies data from register to memory. Similar format to load. Name of operation, register to be stored, base register, offset to select array element. AKA store register in LEGv8.

89
Q

Alignment Restriction

A

Requirement that data be aligned in memory on natural boundaries. e.g. word must start at addresses that are multiples of 4.

90
Q

Spilling Registers

A

Process of putting less frequently used variables into memory. The more commonly used ones are put into registers.

91
Q

Least significant bit

A

Rightmost bit in LEGv8 doubleword.

92
Q

Most significant bit

A

Leftmost bit in LEGv8 doubleword.

93
Q

Signed Load

A

Function is to copy sign repeatedly to fill rest of register (sign extension) but purpose is to place correct representation of num within register.

94
Q

One’s Complement

A

Notation reps most neg value by 10…000 two + most pos value by 01…11 two leaving equal num negs + pos, ending with 2 zeros, 1 pos + 1 neg. Inversion of every bit in pattern.

95
Q

Biased Notation

A

Notation reps most neg value by 00…000 + most pos value by 11…11 with 0 having value 10…00, thereby biasing num such that num plus bias has non neg rep.

96
Q

Instruction Format

A

Form of rep of instruction composed of fields of binary nums.

97
Q

Machine Language

A

Binary rep used for communication within comp system. Numeric version of instructions.

98
Q

Machine Code

A

Sequence of instructions used for comms within comp system.

99
Q

Opcode

A

Field that denotes operation + format of instruction. Basic op of instruction. Rm = 2nd reg source operand, shamt = shift amount, Rn = 1st reg source operand + Rd = reg dest operand, gets result of op.

100
Q

AND/OR/NOT/EOR

A

Logical bit by bit operations. And, Or + Eor have 2 operands, not has 1. And calcs 1 only if 1 in both operands, or calcs 1 if there’s 1 in either operand. Not inverts bits + replaces 1s with 0s and 0s with 1s. Eor calcs exclusive OR of 2 operands. Calcs 1 only if values diff in 2 operands.

1. Architecture & Networks (CSC 1022) (5 decks)

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