Architecture Textbook 2

Question 1

Conditional Branches

Answer 1

Instruction that tests value + allows for subsequent transfer of control to new address in program based on test outcome.

Question 2

Basic Block

Answer 2

Sequence of instructions without branches (except potentially at end) + without branch targets or branch labels (except possibly at start). One of earliest phase of compilation is to break program into these.

Question 3

Condition codes/flags

Answer 3

4 extra bits that record what happened during instruction. Negative (N), zero (Z), overflow (V) + carry (C).

Question 4

Negative (N)

Answer 4

Result that set condition code had 1 in most signif bit.

Question 5

Zero (Z)

Answer 5

Result that set condition code had 0 in most signif bit

Question 6

Overflow (V)

Answer 6

Result that set condition code overflowed.

Question 7

Carry (C)

Answer 7

Result that set condition code had carry out of most signif bit or borrow into most signif bit.

Question 8

Branch Address Table/Branch Table

Answer 8

Table of addresses of alternative instruction sequences. e.g. case/switch statement.

Question 9

Procedure/Function

Answer 9

Stored subroutine that performs specific task based on parameters it’s provided with. e.g. Method.

Question 10

Branch-and-Link Instruction

Answer 10

Instruction that branches to address + simultaneously saves address of following instruction in register.

Question 11

Return Address

Answer 11

Link to calling site that allows procedure to return to proper address. In LEGv8, stored as register.

Question 12

Caller

Answer 12

Program that instigates procedure + provides necessary parameter values.

Question 13

Callee

Answer 13

Procedure that executes series of stored instructions based on parameters provided by caller + returns control to caller.

Question 14

Program Counter (PC)

Answer 14

Register containing address of instruction in program being executed.

Question 15

Stack

Answer 15

Data structure for spilling registers organised as last in first out queue.

Question 16

Stack Pointer

Answer 16

Value denoting most recently allocated address in stack that shows where registers should be spilled/where old register values can be found. In LEGv8, it’s register SP.

Question 17

Push

Answer 17

Add element to stack.

Question 18

Pop

Answer 18

Remove element from stack.

Question 19

Leaf Procedures

Answer 19

Procedures that don’t call others.

Question 20

Global Pointer

Answer 20

Register reserved to point to static area.

Question 21

Procedure Frame/Activation Record

Answer 21

Segment of stack containing procedure’s saved registers + local variables.

Question 22

Frame Pointer

Answer 22

Value denoting location of saved registers + local variables for given procedure. Some ARMv8 compilers use this to point to first doubleword of procedure frame.

Question 23

Text Segment

Answer 23

Segment of UNIX object file that contains machine language code for routines in source file. Home of LEGv8 machine code.

Question 24

Static Data Segment

Answer 24

Above code. Place for constants + other static variables..

Question 25

The Heap

Answer 25

Segment for data structures that grow and shrink. Placed next in memory.

Question 26

Halfwords

Answer 26

16 bit quantities

Question 27

PC-Relative Addressing

Answer 27

Addressing regime in which address is sum of PC + constant in instruction.

Question 28

Addressing Mode

Answer 28

1 of several addressing regimes delimited by their varied use of operands +/or addresses. e.g. immediate addressing, register addressing, base/displacement addressing, PC-relative addressing.

Question 29

Register Addressing

Answer 29

Operand is register.

Question 30

Immediate Addressing

Answer 30

Operand is constant within instruction.

Question 31

Base/Displacement Addressing

Answer 31

Operand is at memory location whose address is sum of register + constant in instruction.

Question 32

Data Race

Answer 32

2 memory accesses form data race if they’re from diff threads to same location, at least 1 is write + occur 1 after another.

Question 33

Assembly Language

Answer 33

Symbolic language that can be translated into binary machine language.

Question 34

Pseudoinstruction

Answer 34

Common variation of assembly language instructions often treated as if it were an instruction in its own right.

Question 35

Symbol Table

Answer 35

Table that matches names of labels to addresses of memory words that instructions occupy.

Question 36

Linker/Link Editor

Answer 36

Systems program that combines independently assembled machine language programs + resolves all undefined labels into executable file. Places code + data modules symbolically in memory, determines addresses of data + instruction labels, then patches internal + external refs.

Question 37

Exectuable File

Answer 37

Functional program in object file format that contains no unresolved refs. Can contain symbol tables + debugging info. Stripped executable doesn’t contain those. Relocation info may be included for loader.

Question 38

Loader

Answer 38

Systems program that places object program in main memory so it’s ready to execute.

Question 39

Dynamically Linked Libraries (DLLs)

Answer 39

Library routines linked to program during execution.

Question 40

Java Bytecode

Answer 40

Instruction from instruction set designed to interpret java programs.

Question 41

Java Virtual Machine (JVM)

Answer 41

Program that interprets java bytecodes. Interpreters improve portability but reduce performance.

Question 42

Just In Time Compiler (JIT)

Answer 42

Compiler that operates at runtime, translating interpreted code segments into native comp code. Preserves portability + improve execution speed compared to JVM.

Question 43

Object Oriented Language

Answer 43

Programming language that is oriented around objects rather than actions, or data vs logic.

Question 44

General Purpose Register

Answer 44

Register that can be used for addresses/data with virtually any instruction.

Question 45

Load-store Architecture/Register Architecture

Answer 45

Instruction set architecture in which all operations are between registers + data memory may only be accessed via loads/stores.