Architecture

Question 1

What is computer architecture?

Answer 1

Science + art of selecting + interconnecting hardware components to create comp that meets functional, performance + cost goals.

Question 2

What is below a program?

Answer 2

Application software written in HLL, system software & the hardware with the processor, memory + I/O controllers.

Question 3

What is system software?

Answer 3

Compiler translates HLL code into machine code + operating system with service code deals with input/output, manages memory + storage, schedules tasks + shares resources.

Question 4

What are the different levels of program code?

Answer 4

High level language, assembly language (textual rep of instructions + hardware representation (bits, encoded instructions + data)

Question 5

What is HLL code?

Answer 5

High level language. Level of abstraction closer to problem domain + provides for productivity + portability.

Question 6

What is an ISA?

Answer 6

Instruction set architecture. Describes aspects of comp architecture visible to low level programmer, including native datatypes, registers, instructions, addressing modes, memory architecture, interrupt + exception handling + I/O organisation.

Question 7

What are the levels of computer architecture?

Answer 7

Abstraction, which helps us deal with complexity by hiding lower level details. ISA (hardware/software interface) then application binary interface (ISA + system software interface) + implementation (details underlying interface)

Question 8

What is the Von Neumann model?

Answer 8

Shows components for all comps. Input, output, memory, datapath + control (sometimes combined as CPU/processor) Transistors found in processor, called chips.

Question 9

What does the datapath do?

Answer 9

Performs operations on data.

Question 10

What does the control do?

Answer 10

Sequences datapath + memory.

Question 11

What does input/output include?

Answer 11

Network adapters for communicating with other comps.

Question 12

What is the processor made up of?

Answer 12

Transistors made of silicon which is a semiconductor + materials added to it to transform its properties. They make up memory.

Question 13

What is yield?

Answer 13

Proportion of working dies per wafer.

Question 14

What is Moore’s Law?

Answer 14

Predicted that num of transistors that can be integrated on die would double every 1.5 to 2 years.

Question 15

What is the memory wall?

Answer 15

Processor performance becomes faster than memory performance. Processing elements become fast + need more data to process but memory speed doesn’t improve as fast.

Question 16

How do we overcome the power wall?

Answer 16

Can improve clock rate without increasing power by using muliprocessors/multicore processors. This means we have multiple processors on each chip. Requires explicitly parallel programming. Compare with instruction level parallelism, hardware executes multiple instructions at once, hidden from programmer. Hard to do as need high performance, load balancing, optimised comms + synchronisation.

Question 17

What is response time?

Answer 17

How long it takes to do a task.

Question 18

What is throughput?

Answer 18

Total work done per unit time.

Question 19

What is the performance equation (n times faster)?

Answer 19

Performance = 1/execution time e.g. performance(x)/performance(y) = execution time(y)/execution time (x) = n times faster

Question 20

What is the percentage change equation?

Answer 20

Percentage change = ((new – old)/old)*100. Positive result indicates increase whilst negative result indicates decrease.

Question 21

What is elapsed time?

Answer 21

AKA system performance, total response time, including processing, I/O, OS overhead, idle time etc.

Question 22

What is CPU time?

Answer 22

AKA CPU performance, time spent processing given job (discounts I/O time, other jobs’ shares). Comprises user CPU time + system CPU time. Diff programs affected differently by CPU + system performance.

Question 23

What is a clock cycle?

Answer 23

Clock period/cycle = duration of clock cycle (in ps) 1/clock rate. Operation of digital hardware is governed by constant rate clock. 1 ms = 10-3 s, 1 us = 10-6 s, 1 ns = 10-9 s, 1 ps = 10-12 s

Question 24

What is clock rate?

Answer 24

Clock frequency/rate = cycles per second (in GHz) 1/clock cycle. 1 kHz = 103 Hz, 1 MHz = 106 Hz, 1 GHz = 109 Hz, 1 THz = 1012 Hz. 1 Hz is 1 cycle per second.

Question 25

What is CPU performance + how is it improved?

Answer 25

CPU performance = CPU clock cycles x clock cycle time = clock cycles/clock rate
Improved by reducing num of clock cycles + increasing clock rate.

Question 26

What is the equation for clock cycles?

Answer 26

Clock cycles = instruction count x cycles per instruction

Question 27

What is the equation for CPU time?

Answer 27

CPU time = instruct count x CPI x clock cycle time = (inst count x CPI)/clock rate

Question 28

How is instruction count determined?

Answer 28

By programmer, ISA & compiler.

Question 29

How is CPI determined?

Answer 29

Average cycles per instruction (CPI) determined by CPU hardware. If diff instructions, have diff CPI. Average CPI affected by instruction mix. CPI varies between programs on given CPU.

Question 30

What does performance depend on?

Answer 30

Product. Minimise product, not isolated terms. E.g. ISA change to decrease instruction count but leads to slower clock.

Question 31

What is MIPS?

Answer 31

Millions of instructions per second. Doesn’t account for diffs in ISAs between comps or diffs in complexity between instructions.

Question 32

What is the equation for MIPS?

Answer 32

instruction count/(execution time x 106) =

Question 33

What is Amdahl’s law?

Answer 33

Improving aspect of comp + expecting proportional improvement in performance. F = fraction sped up + s = speedup on fract. E.g. T(improved) = (T(affected)/improvement factor) + T(unaffected)
Speedup = old time/new time = new rate/old rate.
S = 1/(1-x%) where x% speedup in percentage

Question 34

What is corollary?

Answer 34

Make common case fast.

Question 35

What is the ISA?

Answer 35

Repertoire of instructions supported by processor architecture, diff processor arcs have diff instruction sets but many aspects in common. Early processors had simple instruction sets, simplified implementation, modern processors can have simple instruction sets.

Question 36

What are the types of ISA?

Answer 36

2 types: CISC: Complex Instruction Set Computing. Complex instructions, less instructions per program, more cycles per instruction +/or seconds per cycle. + RISC: Reduced Instruction Set Computing. Simple instructions, more instructions per program, less cycles per instruction +/or seconds per cycle. E.g. x86 (CISC), ARM + MIPS (Microprocessor without Interlocked Pipelined Stages) (both RISC). We deal with ARM (LEGv8).

Question 37

How do we add and subtract?

Answer 37

Use 3 operands (2 sources + 1 dest) ADD a, b, c (a = b + c) or SUB a, b, c (a = b – c). Regularity = simpler implementation + simplicity = higher performance at lower costs. ADD = opcode (operation code). Operands = input/output data (source/dest). ADD f, t0, t1 -> Operands t0 + t1 are temp registers. 1 opcode, 2 inputs, 1 output. 1C statement = multiple instructions.

Question 38

Why don’t we use more complex instructions?

Answer 38

Practical reasons (performance + cost, not computability) + regularity improves both.

Question 39

What are register operands for?

Answer 39

Arithmetic instructions use them, LEGv8 has 32 register files of 64 bits, used for frequently used data. 64 bit data called doubleword, 31 x 64 bit gen purpose registers X0 to X30, reg X31 (XZR) = 0. 32 bit data called word, 31 x 32 bit gen purpose sub-registers W0 to W30. W31 (WZR) = 0.

Question 40

What are the general purpose registers?

Answer 40

X0 – X7 = procedure args/results. X8 = Indirect result location reg. X9 – X15 = Temps. X16 – X17 (IP0 – IP1) = May be used by linked as scratch reg or as temp reg. X18 = Platform reg for platform indep code or as temp reg. X19 – X27 = Saved. X28 (SP) = Stack pointer. X29 (FP) = Frame pointer. X30 (LR) = Link reg (return address).

Question 41

What is the datapath?

Answer 41

Datapath: CPU (datapath + control unit), control sequences datapath + memory, datapath performs ops on data (ALU (Arithmetic + logic unit), registers, interconnections.

Question 42

How is main memory used?

Answer 42

Composite data (arrays, structures, dynamic data) to apply arithmetic ops, load values from mem to regs, store result from reg to mem. Memory is byte addressed (each address identifies 8 bit byte). LEGv8 doesn’t require words to be aligned in mem, except for instructions + stack. E.g. LDUR (load reg from mem) + STUR (store reg in mem) U for unscaled offset (mem address offset provided not scaled).

Question 43

Why are registers better than memory?

Answer 43

Faster to access than memory, operating on mem data requires loads + stores (more instructions to be executed), compiler must use regs for variables as much as possible (only spill to mem for less frequently used variables, register optimisation is important). In CISC, mem to mem, LOAD + STORE incorporated in instructions. In RISC, reg to reg, LOAD + STORE are indep instructions.

Question 44

What are immediate operands?

Answer 44

Constant data specified in instruction, small constants are common, immediate operand avoids load instruction.

Question 45

How are instructions encoded?

Answer 45

In binary (machine code/language). LEGv8 instructions encoded as 32 bit instruction words, small num formats encoding opcode, reg nums.

Question 46

What are R-format instructions?

Answer 46

Register instructions. Instruction fields: Opcode (operation code), Rm (2nd reg source operand), shamt (shift amount, 00000), Rn (1st reg source operand) + Rd (reg dest).
e.g. ADD Rd, Rn, Rm (ADD X9, X20, X21). Machine code: = 8B150289 hex

Question 47

What are D-format instructions?

Answer 47

Data transfer instructions. Load/store instructions: address (constant offset from contents of base reg (+/- 32 doublewords), op2 (expands opcode field), Rn (base reg), Rt (dest (load)/source(store) reg num).
e.g. LDUR Rt, [Rn, addr} (LDUR X9, [X22, #64]

Question 48

What are the different formats of instructions for?

Answer 48

Complicate decoding but allow 32 bit instructions uniformly, keep formats as similar as possible.

Question 49

What are I-format instructions?

Answer 49

Immediate instructions. Rn (source reg) + Rd (dest reg) Immediate field is zero extended.
e.g. ADDI Rd, Rn, imm (ADDI X9, X9, 1)

Question 50

Where are instructions + data stored?

Answer 50

In mem, programs can op on programs (compilers, linkers), binary compatibility allows compiled programs to work on diff comps (standardised ISAs). Instructions for bitwise manipulation (useful for extracting + inserting groups of bits in word)
e.g. If LSL by 3, multiply by 8 because (23). If LSR by 3, divide by 8 because (23).

Question 51

What are shift operations?

Answer 51

R-Format: Shamt (shift amount) Shift left logical (shift left, fill with 0 bits, LSL by I bits multiplied by 2i). Same idea for shift right but divide.
e.g. LSL X11, X19, #4 (X11 = X19 &laquo_space;4 bits).

Question 52

What are AND + OR operations for?

Answer 52

AND useful for masking bits in word, select some bits, clear others to 0. OR/EOR ops (differencing ops, set some bits to 1, leave others unchanged.
Branch to labelled instruction if condition true, otherwise continue sequentially. CBZ reg, L1 (if (reg==0) branch to instruction labelled L1;

Question 53

What are procedure calls?

Answer 53

Procedure calls: Place parameters in register X0 to X7, transfer control to procedure, acquire storage for procedure, perform procedure’s operations, place result in reg for caller, return to place of call (address in X30/LR)

Question 54

What are jump and link and jump register?

Answer 54

Procedure call: jump + link. Puts address of following instruction in X30/LR, jump to target address. Procedure return: jump reg. Copies LR to PC. PC is reg with address of instruction in program being executed.

Question 55

What are the registers reserved on procedure calls?

Answer 55

Regs reserved on procedure calls: X9 – X17 (Temp regs, not preserved by callee (called procedure) on procedure call). X19 – X28 (saved regs, must be preserved on procedure call, if used, callee saves + restores them) Only 8 regs need for parameters X0 – X7. If need more, spill registers for mem.

Question 56

What is the data structure for spilling registers?

Answer 56

Data structure for spilling regs: Stack (LIFO queue, last in, first out), stack pointer (SP, X28, points most recently allocated address in stack), push (adds element to stack), pop (removes element from stack), stack grows from higher to lower addresses. Stack also used for procedure local variables not stored in regs (local arrays, structures).

Question 57

What is a procedure frame?

Answer 57

Procedure frame: segment of stack containing procedure’s saved regs + local variables, frame pointer (FP, X29, points first doubleword of PF).

Question 58

What is the memory layout?

Answer 58

Memory layout : Text (program code), static data (global variables e.g. string), dynamic heap (heap e.g. new), stack (automatic storage).