4 Flashcards
V_il is threshold voltage for n transistor
V_ih is threshold voltage of pmos
Noise margins
Propagation delay is with respect to
Output. T_phl
Propagation average
T_phl + T_plh /2
Rise and Fall time for input can be different from
Rise and fall times in output.
An nmos inverter (not cmos) consists of
A pull up resistor with a nmos as pull down
Pmos inverter consists of
Pmos as pull up and resistor as pull down
The larger the resistor
The larger the area on chip than transistors.
Diode mode configuration of mosfet
Drain and gate of mosfet get shorted to get it to be like a diode or a resistor.
How can resistance be adjusted in a mosfet
Reduce W and L or size of transistor.
CMOS has drawback
Larger area on chip than nmos circuits but cmos allows us to control rise and fall time.
Drawback of nmos circuits
Large power consumption because there is resistance now. P = v^2 / R
In CMOS there is no current (i=0)
So static power of CMOS is 0!! But in reality there is a slight resistance in fets (in picoAmpere range) that cannot be avoided.
Static power =
P_s = VDD ×Idd
Dynamic power loss =
P_d = C×(Vdd^2) ×f
Transient voltage
Voltage range of which power supply oscillates
Dynamic power loss cannot be avoided
Only reduced
Voltage has a bigger role in power consumption and we can always reduce voltage
Voltage scaling is used. We can reduce voltage although we cannot reduce too much since we need a threshold voltage.
With C_l large, slow rise and fall time
With C_l small, fast rise and fall time.
Increasing width in on condition, R is reduced and faster rise and fall time.
Lump capacitor
Combines multiple capacitors into one capacitor. In Power consumption, c represents internal capacitors as well as C_l.
Crowbar current
V shape current. In transition state it turns on every time the switch from 0 to 1 happens. Or leakage current. Faster rise and fall times lead to less area under current and less power.
Pullup network takes circuit to logic 1
Pull down network takes to logic 0
There is a tradeoff between static power and dynamic power consumption.
Decreasing static increases dynamic power.
Lithography
Process using light exposure in which we create a pattern on a silicon wafer (remove silicon dioxide insulation layer)
