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Question 1

Smaller w gives

Answer 1

Higher R_on for the mosfet.

Question 2

W and l are constant once fabricated

Question 3

Ron exists when VGS is equal to threshold.

Question 4

What region do mosfet use in on state

Answer 4

Triode

Question 5

What region do mosfet use for off state

Answer 5

Cutoff

Question 6

Before CMOS nmos and pmos logic gates were individually manufactured.

Question 7

How to reduce capacitance in a mosfet

Answer 7

Make a deeper seperator to increase distance between n- and p- of semiconductor in substrate

Question 8

Tie substrate to source for stuck diagrams if aeperare substrate doesn’t exist.

Question 9

What is polysilicon

Answer 9

A crystal that is doped.

Question 10

What is demorgans theorem

Answer 10

(A&B)! = A! + B!

(A+B)! =

Question 11

What types of circuits do CMOS logic gates consist of

Answer 11

Pull-up and pull-down networks

Question 12

What are combinational circuits?

Answer 12

Logic gates (and nor not etc)

Question 13

What are sequential circuits?

Answer 13

Logic gates + clock signals (clock acts as synchronizer)

Question 14

What two circuits do digital circuits compose of

Answer 14

Combinational and sequential circuits

Question 15

What is the purpose of clock in sequential circuits

Answer 15

Makes sure signal arrives on time and operations are done on time.

Question 16

What are pull up networks composed of

Answer 16

P channel mosfets

Question 17

What are pull down networks composed of

Answer 17

N channel mosfets

Question 18

Where is output on CMOS

Answer 18

Between pullup and pulldown network connection

Question 19

How to create a CMOS logic gate based on boolean logic

Answer 19

1. Analyze and simplify boolean equation y=(A&B)!
2. Draw pull down network by using n channel mosfet.
3. Draw complementary section (pull up network).
4. Connect pull up network to power supply and pull down network to ground.

Question 20

Multiplication in boolean logic means

Answer 20

Series in CMOS pull down network.

Question 21

Addition (or) of boolean logic means

Answer 21

Parallel connection in NMOS pull down network of CMOS.

Question 22

How to convert CMOS pull down network to pull up network.

Answer 22

Series = parallel and parallel = series.

Question 23

N Channel mosfet is off when

Answer 23

Gate voltage is 0.

Question 24

At every junction in a mosfet there is a capacitance.

Question 25

Most dominant capacitance is gate capacitance in mosfet.

Question 26

Capacitors are shortcomings of all speed performance of mosfet.

Question 27

How do you create a CMOS OR gate?

Answer 27

Same as NOR gate, but with an inverter at the output.

Question 28

How do you create a CMOS AND gate?

Answer 28

Same as CMOS NAND, but with an inverter at the output.

Question 29

P channel transistors are larger than n channel transistors.