36. I/O Devices Flashcards
What is true about buses?
The shorter and closer the bus to CPU, the faster it is. The longest and furthest buses are the slowest. The width of bus also defines its speed.
What kind of buses are there?
Memory bus, closest to CPU or integrated into it, connects to CPU.
General I/O bus (for network cards, NVME, videocards), connects to CPU or chipset. Peripheral I/O bus, for slower device, connects to chipset, slowest because its devices don’t require that much speed.
What is canonical I/O device composed of?
First it has some kind of interface for communication with the hardware, this interface is used by OS. Then it has an internal structure, which is responsible for implementing the abstraction the device present to system (actual instructions). Complex devices will include own small CPU, some general purpose memory and other device-specific chips.
What registers does canonical device have?
Status, command, data.
What is programmed I/O?
It’s when CPU is involved with data movement into device’s registers.
What is two-phased approach?
It’s an approach where the CPU polls the device for an operation completion a little bit before giving up and waiting for interrupt. It can improve efficiency when the operations are quite fast so there is no need to wait for interrupt and overload the system with these interrupts.
What is coalescing?
It’s an optimization where device waits for a bit to group the requests before issuing an interrupt.
What is DMA?
Direct Memory Access (DMA) is a specialized hardware device that performs data transfers between I/O devices and main memory without much CPU involvement. The OS configures the DMA by specifying the source, destination, and size of the data. The DMA controller handles the transfer independently and raises an interrupt upon completion to notify the OS. This approach is much more efficient than Programmed I/O (PIO), as it reduces CPU overhead and allows the CPU to focus on more critical tasks.
What are two ways to communicate with I/O devices?
- Explicit I/O instructions. The CPU issues ‘in’ and ‘out’ instructions to send data to registers. These are priviliged.
- Memory-mapped I/O. Hardware makes device registers available if they were memory locations, the CPU then uses usual load/store instructions and hardware then routes them to a device.
How is device-specific implementation hidden from an OS?
The request comes through a POSIX API to a filesystem, which then translates a request into a block-level request to generic block layer. The generic layers in its turn transforms a request into a device driver instruction. The device instruction is a final place which translates driver instructions into hardware-specific instructions.
There is also ‘RAW’ interface which allows to bypass filesystem and operate on the block level.
