19. Paging: TLBs

Question 1

What is TLB? Where is it located?

Answer 1

TLB (translation-lookaside buffer) is located on memory-management unit (MMU) and is simply hardware cache of popular virtual-to-physical address translations

Question 2

What is basic algorithm for TLB?

Answer 2

1. Extract VPN
2. Check if TLB holds translation for this VPN
3. If it does, it’s a cache hit
4. If it does not, consult the page table and put the translation in TLB
5. Retry instruction

Question 3

How does TLB achieve high hit rate?

Answer 3

Due to spatial locality, when several memory references can be in the same page. In this case if page was loaded for element n, the element n+1 will be a hit (if in the same page). TLB also relies on temporal locality.

Question 4

Who handles TLB miss?

Answer 4

It can be either hardware (CISC systems) or OS (RISC systems)

Question 5

What should be considered when OS handles the TLB miss?

Answer 5

Hardware should alter the PC so when return-from-trap instruction is executed, the original instruction is retried. Also OS has to make sure not to cause an infinite loop of TLB misses

Question 6

What is inside TLB?

Answer 6

Usually, 32, 64 or 128 entries. Each entry consists of VPN, PFN and other bits such valid, protection, dirty bit and an address-space identifier

Question 7

How is situation handled when TLB has duplicate VPNs each from different process mapping to different PFNs?

Answer 7

One option is just to flush TLB on each context switch. Another option is to store ASID in TLB and also in CPU register (to know what ASID to lookup)

Question 8

What is formula for effective memory access time?

Answer 8

EMAT=(TLB hit rate×TLB access time)+(TLB miss rate×page table access time)