20. Paging: Smaller Tables Flashcards
If linear page table consumes too much space, why not use just bigger pages? Are there working systems that use bigger pages?
Bigger pages lead to internal framgentation within than page. However, some systems provide an option for a user-process to request a page with bigger size, while still maintaining small size pages as default. This is done to to save space thought, but for TLB to have this entry.
What is usual size of a page?
4KB or 8KB
What are other approaches of constructing page table instead of usual linear page table?
Bigger page sizes, hybrid of segmentation and paging, multi-level page tables
How does hybrid approach work? How does it reduce the memory overhead of simple linear page table?
It’s a hybrid of segmentation and paging. Now each segment (i.e code, stack and heap) would have a different page table and base bounds register (so 3 pairs of registers and 3 page tables). The base and bounds registers are used to indicate start of page table for a segment and its end (how many pages it has). Page table in this case would allocate space only for valid entries
What’s the downside of hybrid approach?
External fragmentation because of varying page table sizes
What is an idea of multi-level page table? What structure does it use?
First, the page table is divided into pages itself so we can allocate or deallocate entire pages of page table. This lead to having only those pages of page table, that are valid i.e contain references to used PFNs. Pages that do not have any valid PTEs are marked invalid and space is not allocated for them.
What is PDE? What does it minimally has?
Page Directory Entry. It’s an entry inside page directory data structure that contains referrences to the second-level page tables which in turn have PTEs inside them pointing to a physical frame number. It minimally has a valid bit and PFN
How is virtual address constructed with MLPT?
Higher bits are for page directory index, the next coming bits are for the page table entry inside this PDE, and the rest is for offset.
What is an inverted page table?
It’s a single page table that holds an entry for each physical page of the system
How is it defined which bits in virtual address will be used for offset, PDEs and PTEs?
First, the offset is calculated based on size of page. Then the remaining number of bits are divided by number of levels in page table
