1.1.2 Processor REMADE (old) Flashcards

1
Q

What size instruction set does RISC processors have?

A

Small instruction set.

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2
Q

How many lines of machine code is each instruction in RISC processors?

How many clock cycles does each instruction take?

A

One line of machine code.

One clock cycle.

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3
Q

What size instruction set does CISC processors have?

A

Large instruction set

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4
Q

How does CISC try to accomplish tasks?

A

In as little lines of machine code as possible.

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5
Q

Where are instructions stored on CISC?

A

Instructions are built into the hardware.

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6
Q

Where are CISC processors used?

A

Microcontrollers and embedded systems.

Laptops and desktop computers made by Intel or AMD

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7
Q

Compare the hardware used in CISC processors to RISC processors.

A

The hardware in CISC processors is more complex than the hardware in RISC processors.

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8
Q

Compare the size and cost of CISC and RISC

A

CISC:

  • Physically larger in size
  • Requires more silicon to make therefore more expensive

RISC:

  • Physically smaller in size
  • Less complex circuitry required and less silicon needed to make therefore cheaper.
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9
Q

Compare the energy consumption of CISC and RISC

A

CISC: Greater energy consumption

RISC: Lower energy requirements, and can go into sleep mode when not actively processing

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10
Q

How will tasks of different complexities fare with CISC or RISC?

A

CISC: More intensive tasks will do better

RISC: Run at lower clock speed, but can perform simple tasks faster than CISC

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11
Q

What is a unique feature of RISC that CISC lacks?

A

RISC can support pipelining.

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12
Q

Give a simplified definition of pipelining.

What is pipelining aimed at?

A

The process completing the FDE cycles of three separate instructions simultaneously.

It is aimed to reduce the amount of the CPU which is kept idle.

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13
Q

What are multi-core CPUs?

A

They have multiple independent cores that can complete instructions separately which results in higher performance.

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14
Q

What are parallel systems?

A

Systems where multiple instructions can be completed at any given time, doesn’t require multiple cores, it can use threading and pipelining instead.

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