1.1.1 Structure And Function Of The Processor

Question 1

What is the ACC?

Answer 1

A special register to temporarily store the results of operations performed by the ALU

Question 2

What are the 3 buses?

Answer 2

Address, control and data

Question 3

What does the address bus do?

Answer 3

This is the bus used to transmit the memory addresses specifying where data is to be sent to or retrieved from. The width of the address bus is proportional to the number of addressable memory locations.

Question 4

What does the data bus do?

Answer 4

This is a bi-directional bus (meaning bits can be carried in both directions). This is used for transporting data and instructions between components.

Question 5

What 6 things does control bus do?

Answer 5

Bus request
Bus grant
Memory write
Memory read
Interrupt request
CPU Clock

Question 6

What 4 things does the ALU perform?

Answer 6

Performs arithmetic and logical operations on data
Arithmetic operations on fixed and floating point numbers
Bitwise shift operations left and right
Boolean logic operations

Question 7

What is cache?

Answer 7

A small and fast but expensive memory in the CPU used to store instructions and data that are accessed regularly

Question 8

What is clock speed?

Answer 8

The frequency at which the internal clock generates signals switching between 0 and 1.

Question 9

What does the clock speed control?

Answer 9

It controls how often instructions are executed and data is fetched

Question 10

What is contemporary processor architecture?

Answer 10

A modern computer architecture combing elements of both von neumann and harvard architectures

Question 11

What is the CU?

Answer 11

A part of the CPU that controls and manages the execution of inctructions.
It sends control signals to coordinate execution and controls the FDE cycle and buses.

Question 12

What does the CIR do?

Answer 12

Holds the current instruction being executed
The contents of the MDR are copied to the CIR if its an instruction
Contains the opcode + operands

Question 13

What is the fetch decode execute cycle?

Answer 13

The process of fetching from memory, decoding and executing the instruction

Question 14

What are the 4 steps of the fetch phase?

Answer 14

Address from the PC is copied to the MAR Instruction held at that address is copied to MDR by the data bus
Simultaneously, the contents of the PC are increased by 1
The value held in the MDR is copied to the CIR

Question 15

What happens in the decode phase?

Answer 15

The contents of CIR are split into operand and opcode

Question 16

What are the advantages of the von neumann architecture?

Answer 16

Cheaper to develop as the control unit is easier to design
Programs can be optimised in size

Question 17

What are the advantages of harvard architecture?

Answer 17

Quicker execution as data and instructions can be fetched in parallel.
Memories can be different sizes, which can make more efficient use of space

Question 18

What is harvard architecture?

Answer 18

A computer architecture that stores data and instructions in seperate memories to allow the next instructuon to be read while data is currently being read or written to.

Question 19

What does the MAR do?

Answer 19

This holds the address of the memory location from which data or an instruction is to be fetched or written to
Send these addresses to memory down the address bus

Question 20

What does the MDR do?

Answer 20

Used to store the data that is: temporarily read from or written to memory
Sometimes known as the memory buffer register (MBR)
All data to and from memory must travel down the data bus and pass through the MDR

Question 21

What does the PC do?

Answer 21

Holds the address of the next instruction to be executed
This could be:
The next instruction in a sequence of instructions
The address to jump to if the current instruction is a command to jump or branch - this would be copied from the current instruction register

Question 22

The PC has a very close relationship with what?

Answer 22

Has a very close relationship with the memory address register. At the start of every new FDE cycle the address held in the PC is copied to the MAR

Question 23

What is a core?

Answer 23

A core is an independent processor that is able to run its own fetch-execute cycle.

Question 24

What can a multi core processor do?

Answer 24

A computer with multiple cores can complete more than one fetch-execute cycle at any given time.

Question 25

Can a dual core processor work twice as fast?

Answer 25

A computer with dual cores can theoretically complete tasks twice as fast as a computer with a single core. However, not all programs are able to utilise multiple cores efficiently as they have not been designed to do so, so this is not always possible.

Question 26

Explain the levels of cache

Answer 26

Level 1 Cache : Very fast memory cells with a small capacity. (2-64KB)
Level 2 Cache: Relatively fast memory cell, with a medium sized capacity. (256KB-2MB)
Level 3 Cache: Much larger and slower memory cell.

Question 27

What is assembly code?

Answer 27

Assembly code uses mnemonics to represent instructions, for example ADD represents addition. This is a simplified way of representing machine code.

Question 28

What is the instruction is assembly langauge split into?

Answer 28

The instruction is divided into operand and opcode in the Current Instruction Register.

Question 29

What does the operand contain?

Answer 29

The operand contains the data or the address of the data upon which the operation is to be performed.

Question 30

What does the opcode specify?

Answer 30

The opcode specifies the type of instruction to be executed.

Question 31

What does the control bus generally do?

Answer 31

This is a bi-directional bus used to transmit control signals between internal and external components. The control bus coordinates the use of the address and data buses and provides status information between system components.

Question 32

What are buses?

Answer 32

Buses are a set of parallel wires which connect two or more components inside the CPU. There are three buses in the CPU: data bus, control bus, and address bus. These buses collectively are called the system bus.

Question 33

What is the width of the bus?

Answer 33

The width of the bus is the number of parallel wires the bus has.

Question 34

What is the width of the bus proportional to?

Answer 34

The width of the bus is directly proportional to the number of bits that can be transferred simultaneously at any given time. buses are typically 8, 16, 32 or 64 wires wide.

Question 35

What is pipelining?

Answer 35

Pipelining is the process of completing the fetch, decode, and execute cycles of three separate instructions simultaneously, holding appropriate data in a buffer in close proximity to the CPU until it’s required.
While one instruction is being executed, another can be decoded and another fetched.

Question 36

What is piplining spilt into?

Answer 36

It is separated into instruction pipelining and arithmetic pipelining.

Question 37

What is instruction pipelining?

Answer 37

Instruction pipelining is separating out the instruction into fetching, decoding, and executing.

Question 38

What is arithmetic pipelining?

Answer 38

Arithmetic pipelining is breaking down the arithmetic operations and overlapping them as they are performed.

Question 39

What is the aim of pipelining?

Answer 39

Pipelining is aimed to reduce the amount of the CPU which is kept idle.

Question 40

What does it mean in regards to a bus request with the control bus?

Answer 40

Bus request: shows that a device is requesting the use of the data bus

Question 41

What does it mean in terms of a bus grant with the control bus?

Answer 41

Bus grant: shows that the CPU has granted access to the data bus

Question 42

What does memory read mean in regards to the control bus?

Answer 42

Memory read: data is read from a specific location to be placed onto the data bus

Question 43

What does memory write mean in terms of the control bus?

Answer 43

Memory write: data is written into the addressed location using this bus

Question 44

What do interrupt requests in terms of the control bus?

Answer 44

Interrupt request: shows that a device is requesting access to the

Question 45

How does the cpu clock relate to the control bus?

Answer 45

CPU Clock: used to synchronise operations

Question 46

What 5 things does the CU do?

Answer 46

It has the following jobs: Controlling and coordinating the activities of the CPU
Managing the flow of data between the CPU and other devices
Accepting the next instruction
Decoding instructions
Storing the resulting data back in memory