1.1.1 Structure and function of the processor Flashcards
ALU and its purpose
Arithmetic logic unit
Carries out the calculations and logical decisions.
CU and its purpose
Control unit sends out signals to coordinate how the processor works.
- Controls the way data moves around the CPU
- controls and monitor the flow of data between the CPU and other components, such as memory, input devices.
- It executes the instructions provided by the program.
Instruction set
The collection of instructions CU can carry out.
It is hard-wired into the CPU when it was designed.
Registers
Tiny areas of extreme fast memory located in the CPU designed for specific purpose.
Needed during processing.
PC
Program counter
Holds the address of the next instruction to be executed.
ACC
Accumulator
1.Stores the calculation result from the ALU.
2. I/O in processor - used as a buffer.
MAR
Memory address register
Holds the address of the memory location are to be read from or written to.
MDR
Memory data register
Holds the data that are to be read from or written to memory.
CIR
Current instruction register
Holds the current instruction being fetched, divided up into operand and opcode.
Buses (def.)
A set of parallel wires which connect components to send signals and data.
3 types of buses and function
Data bus - carries data between the processor and memory
Address bus - carries the address of the memory location being read from or written to.
Control bus - sends control signals from the control unit.
Describe the FDE cycle
- The contents in PC are copied to MAR
- The read signal is sent across the control bus and the contents of the MAR are sent across the address bus
- The contents of the memory location stored in the MAR are then sent across data bus and stored in the MDR
- The contents of the MDR are then copied to the CIR
- PC increment by 1
- The contents of the CIR are sent to CU to be decoded
- Execution according to the instructions
How clock speed affects CPU performance
The FDE process follows the clock speed. Faster clock speed allows more instructions to be performed per second.
But it can be overclocked. And it is limited to smaller problems.
To increase computer power - use newer and faster CPU
How number of cores affects CPU performance
Multicore can handle different tasks simultaneously, improving performance for multi-threading applications.
- This can speed up smaller problems but not enough for larger problems.
- if one core is waiting for another core to finish processing, performance may not be improved.
- Parallel processing isn’t suited to all problems.
Modern CPU has multiple cores that can operate independently.
Cache
A type of high-speed RAM built into processor, used to temporarily hold data and instructions that are likely to be regularly accessed.
How cache affects CPU performance
Cache memory is closer to the CPU than RAM, meaning it can provide data and instructions at aster rate.
Computer with more cache can store more repeated use data, less time the processor as to wait for the instructions.
Cache is costly, so most computers only have a small amount.
Other approaches to improve the performance of computer
- Supercomputers can have multiple processors.
- GPUs can be applied to problems with graphical processing and form co-processor to do scientific calculation. (limited to highly parallelisable problems)
- Pipelining
Pipelining
Pipelining allows one instruction to be fetched as the previous one is being decoded and the one before that is being executed.
limitation - Certain instructions may not be able to be executed until other instructions have been fetched and decoded
Pipelining Q1
Exam Q - explain how pipelining would help a CPU execute the LMC code more quickly
Answer -
《Def of pipelining above + specific explain》 (e.g. LDA could be fetched while OUT is being decoded and INT is being execute.) (e.g. LDA can be fetched as there is no branch instructions/no flush to pipeline.)
Pipelining Q2
Exam Q - descibe one issue BRP may cauese for pipelining
Answer - BRP could be followed by one of two possible instructions, which will only be determined after the line above is executed. Meaning the wrong one may be fetched.
Features for Von Neumann Architecture
AO1/AO2/AO3
- Single CU
- Single ALU
- Instructions are executed in a linear sequence
- Data and instructions share a single memory and one set of data/address bus
=> less complex in design
=> development is cheaper - commonly used in general-purpose computer
=> Allows for dynamic allocation between instruction and data
=> Large programs with small data (games) or small programs with large data can be equally catered
Features of Harvard Architecture
- Dual bus system
- Data and instructions are stored in separate memory spaces
=>Can read/write data and instructions simultaneously
=>Faster execution time
=>More complex as requires two sets of buses
=>expensive development
=>Split memory between instruction and data in a static way (less flexibility), meaning you could ran out of one memory with unused memory in the other area.
=>used in embedded systems and real-time applications - speed advantage & predictable performance
