1.1.1 Structure and function of the processor

Question 1

ALU and its purpose

Answer 1

Arithmetic logic unit
Carries out the calculations and logical decisions.

Question 2

CU and its purpose

Answer 2

Control unit sends out signals to coordinate how the processor works.

1. Controls the way data moves around the CPU
2. controls and monitor the flow of data between the CPU and other components, such as memory, input devices.
3. It executes the instructions provided by the program.

Question 3

Instruction set

Answer 3

The collection of instructions CU can carry out.
It is hard-wired into the CPU when it was designed.

Question 4

Registers

Answer 4

Tiny areas of extreme fast memory located in the CPU designed for specific purpose.
Needed during processing.

Question 5

PC

Answer 5

Program counter
Holds the address of the next instruction to be executed.

Question 6

ACC

Answer 6

Accumulator
1.Stores the calculation result from the ALU.
2. I/O in processor - used as a buffer.

Question 7

MAR

Answer 7

Memory address register
Holds the address of the memory location are to be read from or written to.

Question 8

MDR

Answer 8

Memory data register
Holds the data that are to be read from or written to memory.

Question 9

CIR

Answer 9

Current instruction register
Holds the current instruction being fetched, divided up into operand and opcode.

Question 10

Buses (def.)

Answer 10

A set of parallel wires which connect components to send signals and data.

Question 11

3 types of buses and function

Answer 11

Data bus - carries data between the processor and memory

Address bus - carries the address of the memory location being read from or written to.

Control bus - sends control signals from the control unit.

Question 12

Describe the FDE cycle

Answer 12

1. The contents in PC are copied to MAR
2. The read signal is sent across the control bus and the contents of the MAR are sent across the address bus
3. The contents of the memory location stored in the MAR are then sent across data bus and stored in the MDR
4. The contents of the MDR are then copied to the CIR
5. PC increment by 1
6. The contents of the CIR are sent to CU to be decoded
7. Execution according to the instructions

Question 13

How clock speed affects CPU performance

Answer 13

The FDE process follows the clock speed. Faster clock speed allows more instructions to be performed per second.

But it can be overclocked. And it is limited to smaller problems.

To increase computer power - use newer and faster CPU

Question 14

How number of cores affects CPU performance

Answer 14

Multicore can handle different tasks simultaneously, improving performance for multi-threading applications.

1. This can speed up smaller problems but not enough for larger problems.
2. if one core is waiting for another core to finish processing, performance may not be improved.
3. Parallel processing isn’t suited to all problems.

Modern CPU has multiple cores that can operate independently.

Question 15

Cache

Answer 15

A type of high-speed RAM built into processor, used to temporarily hold data and instructions that are likely to be regularly accessed.

Question 16

How cache affects CPU performance

Answer 16

Cache memory is closer to the CPU than RAM, meaning it can provide data and instructions at aster rate.
Computer with more cache can store more repeated use data, less time the processor as to wait for the instructions.

Cache is costly, so most computers only have a small amount.

Question 17

Other approaches to improve the performance of computer

Answer 17

1. Supercomputers can have multiple processors.
2. GPUs can be applied to problems with graphical processing and form co-processor to do scientific calculation. (limited to highly parallelisable problems)
3. Pipelining

Question 18

Pipelining

Answer 18

Pipelining allows one instruction to be fetched as the previous one is being decoded and the one before that is being executed.

limitation - Certain instructions may not be able to be executed until other instructions have been fetched and decoded

Question 19

Pipelining Q1

Answer 19

Exam Q - explain how pipelining would help a CPU execute the LMC code more quickly
Answer -
《Def of pipelining above + specific explain》 (e.g. LDA could be fetched while OUT is being decoded and INT is being execute.) (e.g. LDA can be fetched as there is no branch instructions/no flush to pipeline.)

Question 20

Pipelining Q2

Answer 20

Exam Q - descibe one issue BRP may cauese for pipelining
Answer - BRP could be followed by one of two possible instructions, which will only be determined after the line above is executed. Meaning the wrong one may be fetched.

Question 21

Features for Von Neumann Architecture
AO1/AO2/AO3

Answer 21

1. Single CU
2. Single ALU
3. Instructions are executed in a linear sequence
4. Data and instructions share a single memory and one set of data/address bus

=> less complex in design
=> development is cheaper - commonly used in general-purpose computer

=> Allows for dynamic allocation between instruction and data
=> Large programs with small data (games) or small programs with large data can be equally catered

Question 22

Features of Harvard Architecture

Answer 22

1. Dual bus system
2. Data and instructions are stored in separate memory spaces

=>Can read/write data and instructions simultaneously
=>Faster execution time
=>More complex as requires two sets of buses
=>expensive development

=>Split memory between instruction and data in a static way (less flexibility), meaning you could ran out of one memory with unused memory in the other area.

=>used in embedded systems and real-time applications - speed advantage & predictable performance