1.1.1 Structure and function of the processor

Question 1

What are CPUs

Answer 1

Central processing units (CPUs) are general purpose processors that execute instructions in a computer system
through the fetch-decode-execute (FDE) cycle.

Each consists of :

An Arithmetic Logic Unit (ALU)

A Control Unit (CU)

Registers

Buses.

Question 2

What is a bus?

Answer 2

A bus is a parallel group of communication channel wires able to transmit data in groups of bits together from one register to another in the processor.

Question 3

What is the Address bus?

Answer 3

The Address bus carries the memory location address of the register where the data is being transmitted to or from.

Question 4

What is the Data Bus?

Answer 4

The Data bus carries the data being transmitted from one register to another between areas of the processor and memory. IS BI-DIRECTIONAL

Question 5

What is the Control Bus?

Answer 5

The Control bus transmits control signals from the CU to allow synchronisation of signals to the rest of the
processor.

Question 6

What is the Arithmetic Logic Unit (ALU)?

Answer 6

Carries out arithmetic calculations and logical decisions.

Acts as a conduit through which all I/O to computer is done and a gateway to and from the processor.

The results of its calculations are stored in the Accumulator (ACC).

Question 7

What is the Accumulator (ACC)?

Answer 7

Temporary storage of intermediate results in the ALU holds the data currently being processed during calculations. Deals with the I/O data in the processor and is used as a buffer. All arithmetic and logical operations use the ACC.

Question 8

What is the Control Unit (CU)?

Answer 8

Decodes and manages the execution of instructions using control signals to coordinate movement of data
through the processor and other parts of the computer.

Sends out signals to coordinate how the processor works.

Synchronises actions using inbuilt clock.

Controls FDE cycle and buses.

Question 9

What is the Current Instruction Unit (CIR)?

Answer 9

Holds the most recently fetched data/instructions to be decoded and executed into opcode and operand. Instruction contents are split into 2 component parts. Opcode is first part of instruction decoded so CU knows what to do and remainder of the instruction content is address of data to be used with the operation or actual data if immediate operand is used. Operand is coped to MAR if it is an address for accessing data to ACC or to MDR if it is data. Sends address to PC for jump instruction and determines the type of addressing to be used.

Question 10

What is the Memory Address Register (MAR)?

Answer 10

Contains the address of the next instruction or of the next location to be accessed in memory copied from PC or the address of next data item to be used copied from operand part of instruction from CIR.

Question 11

What is the Memory Data Register (MDR)?

Answer 11

Contains the instructions of the memory location address specified in the MAR when being transferred between memory and processor. Receives data currently being used by the processor from memory location in address part of ACC. Acts as a buffer and copies data/instructions to CIR.

Question 12

What is the Program Counter (PC)?

Answer 12

It controls the sequence in which the instructions are retrieved and executed and stores the address of the next instruction to be processed. Value is then sent to the MAR and the PC is incremented by 1 each FDE cycle after being read and is changed to address held in CIR if the operation is a Jump.

Question 13

What is the General Purpose Register (GPR)?

Answer 13

Used to temporarily store data being used rather than sending data to and from the comparatively much slower memory.

Question 14

What happens in the ‘fetch’ stage in the fetch-decode-execute cycle?

Answer 14

The next instruction is fetched from the address held by PC in main memory into the processor.

PC passes this address to MAR which provides the location sent along the address bus.

PC is incremented in each cycle and the fetch signal is sent on the control bus.

The contents of the memory location are sent from memory to the processor on the data bus and stored in the
MDR.

The contents of the MDR and ACC are sent to the ALU and the result is stored back in the ACC.

Question 15

What happens in the “decode” stage in the fetch-decode-execute cycle?

Answer 15

Load instruction from address in MAR pointed to MDR.

The instruction is copied from MDR to CIR.

The instruction is decoded into opcode and operand by the CU in the CIR.

Question 16

What happens in the “execute” stage in the fetch-decode-execute cycle?

Answer 16

The appropriate instruction opcode is carried out on the operand by the processor.

Question 17

What are the three factors that affect the speed/performance of a CPU.

Answer 17

Clock speed, Number of cores, Cache Memory.

Question 18

What is clock speed?

Answer 18

The clock controls the process of executing instructions and fetching data.
- Processors have increasingly large clock speeds and can be overclocked to give more cycles per second so more instructions
can be executed per second so the program takes less time to run.
- Increased clock speed is limited to smaller problems. Even doubling the clock speed would only halve the time taken.

Question 19

What is a core?

Answer 19

Each core is a distinct processing unit on the CPU.
- Processors can have multiple cores to speed up smaller problems
- When multitasking, different cores can run different applications. Multiple cores can also work on the same
problem.

Question 20

What is cache memory?

Answer 20

This is small memory that works much faster than main memory.
- By anticipating the data/instructions that are likely to be regularly accessed , the overall speed at which the
processor operates can be increased.

Question 21

What levels of cache are there?

Answer 21

Level 1 cache is extremely fast but small (2-64kb)

Level 2 cache is fairly fast and medium (256kb-2mb)

Level 3 cache is slow but has more storage but is uncommon

Question 22

What is pipelining?

Answer 22

Pipelining would allow one instruction to be fetched as the previous one is being decoded and the one before that is being executed.
- Jump instructions do not pipeline well as they could be followed by one of many instructions determined at execution. This means the wrong one may be fetched or decoded so the pipeline would need to be flushed.

Question 23

What are three types of computer architectures?

Answer 23

Von Neumann Architecture
Harvard Architecture
Contemporary Processor Architecture

Question 24

What is the Von Nuemann Architecture?

Answer 24

Single processor CU manages program control.

Uses FDE cycle to execute one instruction at a time in a linear sequence.

Program and data stored together in same memory format.

Simple OS and easy to program but slow processing large sets of data.

Question 25

What is the Harvard Architecture?

Answer 25

Data/instructions are stored in separate memory units with separate buses.

So while data is being written to or read from the data memory, the next instruction can be read from the
instruction memory.

Question 26

What is the Contemporary Processor Architecture?

Answer 26

Modern high-performance CPU chips incorporate aspects of both architectures.