1.1.1 - structure and function of the processor

Question 1

control unit (CU)

Answer 1

• Controls and coordinates activities of CPU.
• Directs flow of data between CPU and other devices.
• Decodes instructions.

Question 2

bus

Answer 2

A set of parallel wires connecting two or more components of a computer.

Question 3

address bus

Answer 3

• Sends address of data from CPU to memory.
• Unidirectional

Question 4

data bus

Answer 4

• Moves data between main memory and CPU.
• Bidirectional

Question 5

control bus

Answer 5

• Sends control signals.
• Bidirectional

Question 6

arithmetic logic unit (ALU)

Answer 6

Performs arithmetic and logical operations on data.

Question 7

registers

Answer 7

Small, special memory cells that operate at very high speed. Very specific roles.

Question 8

program counter (PC)

Answer 8

Holds the address of the next instruction to be executed.

Question 9

current instruction register (CIR)

Answer 9

Holds the current instruction being executed.

Question 10

memory address register (MAR)

Answer 10

Holds the address of the memory location from which data is to be fetched or written to.

Question 11

memory data/buffer register (MDR)

Answer 11

Temporarily stores the data read from or written to memory.

Question 12

Name the 2 parts of an instruction.

Answer 12

• opcode
• operand

Question 13

stages of fetch stage

Answer 13

1- Address of next instruction copied from PC to the MAR.
2- Instruction held at that address is copied to MDR.
3- PC is incremented.
4- contents of MDR copied into CIR.

Question 14

stages of decode phase

Answer 14

• Instruction in CIR is decoded.
• Opcode determines types of instruction and hardware
• Operand hold address of data or the actual data.

Question 15

stages of execute stage

Answer 15

• Appropriate instruction/opcode is carried out on the operand.

Question 16

Name 3 factors affecting processor performance.

Answer 16

• clock speed
• number of cores
• amount and type of cache

Question 17

How does clock speed affect processor performance?

Answer 17

The greater
the clock speed, the faster instructions will be executed.

Question 18

How does the number of cores affect processor performance?

Answer 18

Each core is theoretically able to process a different instruction at the same time with its own
fetch-execute cycle. However, the software may not always be able to take full advantage of multiple processors.

Question 19

How does amount and type of cache affect processor performance?

Answer 19

Since cache is inside the CPU, fetching data from cache is much quicker than fetching it from main memory.

Question 20

pipelining

Answer 20

Without pipelining, the steps in the Fetch-Execute cycle take place one after the other. Using pipelining, the computer architecture allows the next instructions to be fetched at the same time as the processor is performing arithmetic or logic operations, holding them in a buffer close to the processor until the instruction can be performed

Question 21

Name the 2 pipelines.

Answer 21

1- instruction pipeline
2- arithmetic pipeline

Question 22

instruction pipeline

Answer 22

Consists of the stages in which an instruction is moved through the processor, including its being fetched, buffered and then executed.

Question 23

arithmetic pipeline

Answer 23

Represents the parts of an arithmetic operation that can be broken down and overlapped as they are performed.

Question 24

Explain why pipelining can improve the performance of the processor. [2]

Answer 24

• reduces latency
• an instruction can be fetched while another is decoded
• all parts of the processor can be used at any instance in time.

Question 25

Define the stored program concept.

Answer 25

Machine code instructions are fetched and executed serially by a processor that performs arithmetic and logical operations.

Question 26

4 features of Von Neumann architecture

Answer 26

1- Data and instructions share the same memory.
2- One bus is used to transfer data and instructions.
3- Programs can be optimised in size.
4- Used in conventional processors in PCs and servers.

Question 27

4 features of Harvard architecture

Answer 27

1- Instructions and data are held in separate memories.
2- Parallel data and instruction buses may be used.
3- Programs tend to be large.
4- Used in digital signal processing (DSP) and embedded systems.

Question 28

accumulator

Answer 28

• Temporarily holds the results of calculations by the ALU.
• I/O in processor used as buffer/ gateway.

Question 29

Explain two reasons why software designed for other companies’ may not work other hardware.

Answer 29

• Different processors with different instruction sets.
• Different OS that may make different system calls.

Question 30

Name 3 features of Von Neumann architecture. (3)

Answer 30

• data and instructions stored together
• one instruction at a time
• uses FDE cycle

Question 31

array processor architecture

Answer 31

• SIMD
• many ALUs