1.1.1 Structure and function of the processor Flashcards
1.1.1 A)
What does the CU(control unit) do ?
The CU ππ¨π¨π«ππ’π§ππππ¬ all the activities in the cpu
directs the flow of data between cpu and other components
- [ ] Decodes and controls bus CU
1.1.1 A)
What does the ALU(arithmetic and logic unit) do?
completes all Arithmetic and logical operations
can preform data shifts within a register
1.1.1 A)
What is a register
A small memory cell operating at high speed , temp store of data
1.1.1 A)
Name 5 registers inside the cpu
program counter (pc)
current instruction register (cir)
memory address register (mar)
memory data register (mdr)
accumulator
1.1.1 A)
what does the program counter do?
holds the address of the next instruction
to be executed
1.1.1 A)
what does the memory address register do?
holds address of location that data is to be read from or written too in the main memory
1.1.1 A)
what does the memory data register do?
temp holds data thats been read from or written too the main memory
1.1.1 A)
what does the current instruction register do?
holds the current instruction
decodes the instruction by turning it into opcode and operand
1.1.1 A)
What is the difference between opcode and operand example ADD#3
operation code is the βaddβ
operand is the value β#3β
1.1.1 A)
what does the accumulator do?
temp stores data while calculations are being carried out
I/O in processors used as a buffer / gateway
1.1.1 A)what is a bus
what are the 3 buses
a set of parallel wires connecting two or more components inside the cpu
address
data
control
1.1.1 A)
whats the width of the βbusβ
Width of the bus is the number of parallel wires the width is directly proportional to the # of bits that can be transferred simultaneously
1.1.1 A)
describe the address bus
unidirectional
Transmits the memory addresses specifying where data is send too or received from
width of bus directly proportional to # of addressable locations
1.1.1 A)
describe the data bus
bidirectional
carries binary data around the cpu/computer (around the main memory, mm > mdr)
1.1.1 A)
describe the control bus
bidirectional
control lines ensure that the use of data and address buses by different components doesnβt lead to conflict
transmits control signals between in/external components uses other buses to provide status
example of control lines
- bus request - device requesting to use data bus
- bus grant - grants permission to use data bus
- memory r/w - data r/w to specific locations
- clock - to sync operations
1.1.1 A)
what does Assembly language use to represent machine code instructions
Mnemonics : for example LDA is a mnemonic for load is represnts instructions that are a representation of machine code
1.1.1 B)
describe the fetch phase in the fde cycle
address of the next instruction is copied from the pc > mar
the instruction held at that address(in the main memory ) is copied onto the mdr via the data bus
simultaneously +1 on the pc so holds the address of the next instruction
content of the mdr is copied onto the cir
1.1.1 B)
describe the decode phase in the fde cycle
instruction held at cir instruction decoder splits it up into opcode and operand
opcode tells you type of instruction and what hardware to use
operand if address copied to mar , if data copied to mdr passed through alu/acc
1.1.1 B)
describe the execute phase in the fde cycle
appropriate opcode is carried out on the operand
1.1.1 C)
The factors affecting the performance of the CPU
clock speed
number cores
amount / type of cache
1.1.1 C)
explain clock speed
clock speed is the number of cycles a CPU performs per second
system clock speed generated 0 and 1s synchronising CPU operations
cpu cannot operate faster then clock cycle 0>1>0
1.1.1 C)
explain how # of cores effects performance
core is an independent processor able to do its own fde cycle
multicore is able to process a multiple instructions on its own fde cycle simultaneously
however not all software is able to take full advantage of more cores
explain how amount / type of cache effects performance
cache is a small amount of expensive very fast memory
holds instructions that are likely to be reused
3 levels of cache
level 1 cache extremely fast but small
level 2 fairly fast medium sized
level 3 some cpu have
1.1.1 D
how is pipelining in a processor used to improve
efficiency
process of completing fde cycle on 3 diff instructions simultaneously . holding data in a buffer close to cpu till required
pipelining aims to reduce the idle time of cpu. separates code in fetch, decode and execute .
What is Instructional pipelining
The pipeline will prefetch the next instruction and data and store it in a register
as one instruction leaves the cir the next is read to be loaded and executed
at any given point there will be an instruction in every phase of fde
What is arithmetic pipelining
Divides up an arithmetic operation into its individual steps
each step overlapping the next
1.1.1 E
what are the three types of architecture
von Neumann, Harvard , contemporary
explain von Neumann architecture
-used in processors in pcβs , severs embedded systems and is for only control
- data / instructions are shared memory
- one bus transfers data and instructions
- program optimised in size
- single cu, alu
explain Harvard architecture
-digital signal processing in embedded systems audio , speech
- data and instructions not shared separate memory
- parallel data / instruction buses
-programs tend to be larger
- allows for optimise the size of sells and their buses depending on their needs more eff use of space
contemporary architecture
modern cpu use both von and Harvard
eg splitting the cache into data and instructions (Harvard) but having the main memory data and instruction shard
