1.1.1 Structure and function of the processor

Question 1

1.1.1 A)
What does the CU(control unit) do ?

Answer 1

The CU 𝐜𝐨𝐨𝐫𝐝𝐢𝐧𝐚𝐭𝐞𝐬 all the activities in the cpu
directs the flow of data between cpu and other components

• [ ] Decodes and controls bus CU

Question 2

1.1.1 A)
What does the ALU(arithmetic and logic unit) do?

Answer 2

completes all Arithmetic and logical operations
can preform data shifts within a register

Question 3

1.1.1 A)
What is a register

Answer 3

A small memory cell operating at high speed , temp store of data

Question 4

1.1.1 A)
Name 5 registers inside the cpu

Answer 4

program counter (pc)
current instruction register (cir)
memory address register (mar)
memory data register (mdr)
accumulator

Question 5

1.1.1 A)
what does the program counter do?

Answer 5

holds the address of the next instruction
to be executed

Question 6

1.1.1 A)
what does the memory address register do?

Answer 6

holds address of location that data is to be read from or written too in the main memory

Question 7

1.1.1 A)
what does the memory data register do?

Answer 7

temp holds data thats been read from or written too the main memory

Question 8

1.1.1 A)
what does the current instruction register do?

Answer 8

holds the current instruction
decodes the instruction by turning it into opcode and operand

Question 9

1.1.1 A)
What is the difference between opcode and operand example ADD#3

Answer 9

operation code is the “add”
operand is the value “#3”

Question 10

1.1.1 A)
what does the accumulator do?

Answer 10

temp stores data while calculations are being carried out
I/O in processors used as a buffer / gateway

Question 11

1.1.1 A)what is a bus
what are the 3 buses

Answer 11

a set of parallel wires connecting two or more components inside the cpu
address
data
control

Question 12

1.1.1 A)
whats the width of the “bus”

Answer 12

Width of the bus is the number of parallel wires the width is directly proportional to the # of bits that can be transferred simultaneously

Question 13

1.1.1 A)
describe the address bus

Answer 13

unidirectional
Transmits the memory addresses specifying where data is send too or received from
width of bus directly proportional to # of addressable locations

Question 14

1.1.1 A)
describe the data bus

Answer 14

bidirectional
carries binary data around the cpu/computer (around the main memory, mm > mdr)

Question 15

1.1.1 A)
describe the control bus

Answer 15

bidirectional
control lines ensure that the use of data and address buses by different components doesn’t lead to conflict
transmits control signals between in/external components uses other buses to provide status
example of control lines
- bus request - device requesting to use data bus
- bus grant - grants permission to use data bus
- memory r/w - data r/w to specific locations
- clock - to sync operations

Question 16

1.1.1 A)
what does Assembly language use to represent machine code instructions

Answer 16

Mnemonics : for example LDA is a mnemonic for load is represnts instructions that are a representation of machine code

Question 17

1.1.1 B)
describe the fetch phase in the fde cycle

Answer 17

address of the next instruction is copied from the pc > mar
the instruction held at that address(in the main memory ) is copied onto the mdr via the data bus
simultaneously +1 on the pc so holds the address of the next instruction
content of the mdr is copied onto the cir

Question 18

1.1.1 B)
describe the decode phase in the fde cycle

Answer 18

instruction held at cir instruction decoder splits it up into opcode and operand
opcode tells you type of instruction and what hardware to use
operand if address copied to mar , if data copied to mdr passed through alu/acc

Question 19

1.1.1 B)
describe the execute phase in the fde cycle

Answer 19

appropriate opcode is carried out on the operand

Question 20

1.1.1 C)
The factors affecting the performance of the CPU

Answer 20

clock speed
number cores
amount / type of cache

Question 21

1.1.1 C)
explain clock speed

Answer 21

clock speed is the number of cycles a CPU performs per second
system clock speed generated 0 and 1s synchronising CPU operations
cpu cannot operate faster then clock cycle 0>1>0

Question 22

1.1.1 C)
explain how # of cores effects performance

Answer 22

core is an independent processor able to do its own fde cycle
multicore is able to process a multiple instructions on its own fde cycle simultaneously
however not all software is able to take full advantage of more cores

Question 23

explain how amount / type of cache effects performance

Answer 23

cache is a small amount of expensive very fast memory
holds instructions that are likely to be reused
3 levels of cache
level 1 cache extremely fast but small
level 2 fairly fast medium sized
level 3 some cpu have

Question 24

1.1.1 D
how is pipelining in a processor used to improve
efficiency

Answer 24

process of completing fde cycle on 3 diff instructions simultaneously . holding data in a buffer close to cpu till required
pipelining aims to reduce the idle time of cpu. separates code in fetch, decode and execute .

Question 25

What is Instructional pipelining

Answer 25

The pipeline will prefetch the next instruction and data and store it in a register
as one instruction leaves the cir the next is read to be loaded and executed
at any given point there will be an instruction in every phase of fde

Question 26

What is arithmetic pipelining

Answer 26

Divides up an arithmetic operation into its individual steps
each step overlapping the next

Question 27

1.1.1 E
what are the three types of architecture

Answer 27

von Neumann, Harvard , contemporary

Question 28

explain von Neumann architecture

Answer 28

-used in processors in pc’s , severs embedded systems and is for only control
- data / instructions are shared memory
- one bus transfers data and instructions
- program optimised in size
- single cu, alu

Question 29

explain Harvard architecture

Answer 29

-digital signal processing in embedded systems audio , speech
- data and instructions not shared separate memory
- parallel data / instruction buses
-programs tend to be larger
- allows for optimise the size of sells and their buses depending on their needs more eff use of space

Question 30

contemporary architecture

Answer 30

modern cpu use both von and Harvard
eg splitting the cache into data and instructions (Harvard) but having the main memory data and instruction shard