1.1.1 structure and function of processor

Question 1

purpose of CPU

Answer 1

fetch, decode and execute instructions (FDE)

Question 2

CPU contains

Answer 2

control unit
ALU
system buses
dedicated registers

Question 3

control unit

Answer 3

COORDINATE the activity of all components(1m)
control signals sent along the control bus

Question 4

what does control signal contain

Answer 4

memory read
memory write
bus request
bus grant
clock
(memorise 2 only)

Question 5

what are system buses

Answer 5

series of connectors that transfer signals between internal components
(copper wires on the motherboard)

-control
-address
-data

Question 6

control bus

Answer 6

transmit control signals from the control unit (to other parts of the processor)
(bidirectional)

Question 7

data bus

Answer 7

carries data from one place to another (bidirectional)

width defined by number of wires or lines it contains

bottleneck would occur if data is not wide enough for word

Question 8

address bus

Answer 8

carries the location of address where the data is going(from processor to memory- unidirectional)

width of address bus determines the max possible memory address of system
e.g. 8-bit address bus= 2^8 =256 max memory address

Question 9

what are the direction of buses

Answer 9

control bus: bidirectional
data bus: bidirectional
address bus: unidirectional

Question 10

ALU

Answer 10

arithmetic-logic unit
-arithmetic operations: +,-,*, /
-logical operations: AND, OR, NOT, XOR
-shift operations: move bits L or R within a register

Question 11

register

Answer 11

special memory that operate at a very high speed
all memory that holds temporarily

the 5 dedicated registers:
-PC
-CIR
-MAR
-MDR
-accumulator

Question 12

PC

Answer 12

program counter: hold memory address of NEXT instruction

Question 13

CIR

Answer 13

current instruction register: holds current instruction, which is split into opcode and operand

Question 14

MAR

Answer 14

hold address in memory where process is required to fetch or store data

OR

holds address of instruction from PC
holds address of data from CIR

Question 15

MDR

Answer 15

temporarily holds data/instruction moving between the processor and main memory

act as buffer

Question 16

accumulator

Answer 16

results from the ALU(calculations) temporarily stored

also a register

Question 17

FDE cycle

Answer 17

PC->MAR->(memory)->MDR and PC +1 -> CIR -> (CU) -> MAR (operand)/MDR(opcode)

Question 18

machine code

Answer 18

binary code

Question 19

word

Answer 19

memory that is divided up internally into equal units
length of 8,16,32,64 bits (depends on processor)
each word has its own specific address

Question 20

clock speed

Answer 20

a clock keep regular tick/ clock pulse in the background

more ticks per second, faster the computer can do the FDE cycle

Question 21

number of cores

Answer 21

each core is THEORETICALLY able to process a different instruction at the same time and carry out their own FDE cycle (depends on the program, e,g. google chrome) ;making quad-core computer faster

Question 22

cache

Answer 22

levels: CPU register>L1 cache >L2 cache

higher the level, close to CPU, faster it is, less cache memory it has

cache memory is split into instruction cache and data cache , so they can be fetched simultaneously

Question 23

pipelining

Answer 23

fetch one instruction, decode the previous instruction , execute the instruction before the previous one AT THE SAME TIME

Question 24

von neumann

Answer 24

same memory location for data and instruction
single system bus ->bottleneck
same word size

Question 25

harvard

Answer 25

-separate memory location for data and instruction
-different system bus
-more complex in circuit

used with embedded systems and DSP

Question 26

contemporary processor architectures

Answer 26

incorporate both von neumann and harvard
examples:
-distributed computing
-SIMD
-MIMD