1.1.1 structure and function of processor Flashcards
purpose of CPU
fetch, decode and execute instructions (FDE)
CPU contains
control unit
ALU
system buses
dedicated registers
control unit
COORDINATE the activity of all components(1m)
control signals sent along the control bus
what does control signal contain
memory read
memory write
bus request
bus grant
clock
(memorise 2 only)
what are system buses
series of connectors that transfer signals between internal components
(copper wires on the motherboard)
-control
-address
-data
control bus
transmit control signals from the control unit (to other parts of the processor)
(bidirectional)
data bus
carries data from one place to another (bidirectional)
width defined by number of wires or lines it contains
bottleneck would occur if data is not wide enough for word
address bus
carries the location of address where the data is going(from processor to memory- unidirectional)
width of address bus determines the max possible memory address of system
e.g. 8-bit address bus= 2^8 =256 max memory address
what are the direction of buses
control bus: bidirectional
data bus: bidirectional
address bus: unidirectional
ALU
arithmetic-logic unit
-arithmetic operations: +,-,*, /
-logical operations: AND, OR, NOT, XOR
-shift operations: move bits L or R within a register
register
special memory that operate at a very high speed
all memory that holds temporarily
the 5 dedicated registers:
-PC
-CIR
-MAR
-MDR
-accumulator
PC
program counter: hold memory address of NEXT instruction
CIR
current instruction register: holds current instruction, which is split into opcode and operand
MAR
hold address in memory where process is required to fetch or store data
OR
holds address of instruction from PC
holds address of data from CIR
MDR
temporarily holds data/instruction moving between the processor and main memory
act as buffer
accumulator
results from the ALU(calculations) temporarily stored
also a register
FDE cycle
PC->MAR->(memory)->MDR and PC +1 -> CIR -> (CU) -> MAR (operand)/MDR(opcode)
machine code
binary code
word
memory that is divided up internally into equal units
length of 8,16,32,64 bits (depends on processor)
each word has its own specific address
clock speed
a clock keep regular tick/ clock pulse in the background
more ticks per second, faster the computer can do the FDE cycle
number of cores
each core is THEORETICALLY able to process a different instruction at the same time and carry out their own FDE cycle (depends on the program, e,g. google chrome) ;making quad-core computer faster
cache
levels: CPU register>L1 cache >L2 cache
higher the level, close to CPU, faster it is, less cache memory it has
cache memory is split into instruction cache and data cache , so they can be fetched simultaneously
pipelining
fetch one instruction, decode the previous instruction , execute the instruction before the previous one AT THE SAME TIME
von neumann
same memory location for data and instruction
single system bus ->bottleneck
same word size
