1.1.1 Processors, input, output and storage Flashcards

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1
Q

Computer

A

A computer can process an input from a user in order to reach an output

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2
Q

CPU

A

Central processing unit

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3
Q

What does a CPU design depend on

A

What it is being used for

e.g. phone is smaller than a PC and is battery powered without a fan so it needs a smaller CPU with less functions

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4
Q

Components of a CPU

A

Control Unit
Buses
Arithmetic Logic Unit
Designated Registers

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5
Q

Control unit

A

Processes instructions for the CPU

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6
Q

Buses

A

Move signals around
Consist of connectors that transfer signals between components
8/16/32/64 lines

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7
Q

3 types of bus

A

Address bus - where it is going ; CPU to RAM
Data bus - carries the data around ; both ways
Control bus - controls data instructions ; both ways

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8
Q

Arithmetic logic unit

A

Carries out arithmetic and outputs - stores results in the accumulator

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9
Q

CIR

A

Current instruction register

Holds the current instruction that is being followed

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10
Q

PC (register)

A

Program counter

Memory address of the next instruction

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11
Q

MAR

A

Memory address register

Holds the address of where data is being read/written

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12
Q

MDR

A

Memory data register

Holds data between processor and memory

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13
Q

AC

A

Accumulator

Stores the result of logical calculations

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14
Q

What must you call registers by?

A

Their full names - NO ACRONYMS

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15
Q

Fetch

A

CPU fetches data and stores in registers

  1. PC transfers address of next instruction to MAR
  2. Instruction from that address is carried to MDR
  3. Simultaneously PC value increases by 1
  4. Contents of MDR are transferred to CIR
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16
Q

Decode

A
  1. Instruction held in CIR is decoded
  2. Split into operand and opcode to define the type of instruction and acquire any additional data
  3. Passed to ALU
17
Q

Execute

A
  1. Instruction is executed and result stored in accumulator or memory
18
Q

Operand and opcode

A

opcode has the instruction

operand has the data and address.

19
Q

Words

A

The equal units memory is divided into, usually 8/16/32/64 bits
Each has a separate memory address

20
Q

Address bus

A

The width determines the maximum possible memory addresses (2 to the power of width addresses)

21
Q

Hexadecimal machine code instruction

A

8 bits opcode - 6 instruction, 2 clarify what

8 bits operand

22
Q

Factors affecting performance

A

Clock speed
Number of core
Cache memory
Buses

23
Q

How does clock speed affect performance?

A

It increases the speed of the fetch/decode/execute cycle.
The faster clock speed the more instructions executed per second.
You can overclock if the clock speed is too high

24
Q

How does the number of cores affect performance?

A

They can process more instructions simultaneously

Parallel processing - where multiple cores work on different elements of the same task to complete it quicker

25
Q

Cache memory

A

A small amount of superfast memory that stores recent data and instructions
Level 1 cache smaller but faster, cores share level 2
More allows for better performance

26
Q

How can buses affect performance?

A

A bigger address bus allows you to have more address locations, storing more data and instructions

27
Q

Methods to improve the performance of a computer

A

Changing CPU for clock speed/ more cores/ more cache
More or faster RAM
Change graphics card
SSD (Solid state drive)

28
Q

Pipelining

A

Overlapping stages of the F/D/E cycle to improve performance
One line is executed as the next is decided and the one after that fetched
Data is held in a buffer

29
Q

Issues with pipelining

A

Conditionals from instructions you have executed may mean you now need different instructions, negating the gain by fetching and decoding others before.

30
Q

Register definition

A

Small memory cells that operate at a higj speed. They store data and operations are carried out on data in them

31
Q

Clock

A

An electronic device which generates signals, switching between 0 and 1. The clock speed is measured in Hz

32
Q

Core

A

An independent processor able to carry out its own F/D/E cycle