1.1.1 Flashcards
Arithmetic Logic Unit ( ALU )
Carries out calculations and logical decisions
Control Unit ( CU )
Manages operations within the CPU such as decoding instructions and controlling buses
Registers
Small memory cells that operate at very high speeds and are used to temporarily store data
Program Counter ( PC )
Holds the address of the next instruction to be executed and is incremented with each cycle of the FDE cycle
Accumulator ( ACC )
Stores the results of calculations made by the ALU
Memory Address Register ( MAR )
Stores the address of the next instruction or data to be read from or written to
Memory Data Register ( MDR )
Temporarily stores data that has been read or needs to be written
Current Instruction Register ( CIR )
Holds the current instruction being executed and is seperated into operand and opcode
Buses
Set of parallel wires which connect components in the CPU together
Bus Width
Number of parallel wires the bus has
Data Bus
Transmit data between areas of the processors
Address Bus
Used to carry the address to which the data is being transmitted
Control Bus
Used to send control signals from the control unit to other parts of the processor
Fetch
Address from PC is copied to the MAR
⬇️
Instruction in MAR is copied to the MDR
⬇️
Value held in MDR is copied to CIR
Decode
Contents of CIR are sent to the CU
⬇️
CU then decodes the instruction
Execute
The processor carries out the instruction
Clock Speed
Clock speed means cycles per second
⬇️
The higher the clock speed , the less time a program will take to load
Cache Memory
Cache memory is the CPU’s onboard memory
⬇️
Instructions fetched from main memory are copied to the cache , so if required again they can be accessed quicker
Multiple Cores
Each core is an independent processor able to carry out its own FDE cycle
⬇️
Allowing the ability to multitask
Pipelining
The process of completing FDE cycle of three separate instructions simultaneously
⬇️
Reduces the amount of the CPU that is kept idle
Von Neumann Architecture
Uses a single control unit
Stores data and instructions in the same memory
Harvard Architecture
Data and instructions are stored in separate memory units with separate buses
Fetch-Decode-Execute Cycle
The sequence of operations that are completed in order to execute an instruction
