Week 7 & 9 - ISA + Assembly Flashcards
What is ISA?
set of instructions and binary encodings of machine-level programs
Interface between software and hardware.
How are different types of operands written?
constant, register, memory
constant - preceded by the $ sign
register - mov %rsp, %rbp
memory - mpv -0x4(%rbp), %eax
$ox2 is literally hex ox2
(r) substract 0x4 from %rbp and then m. lookup
How are stack pointer register, frame pointer register (base pointer) and instruction pointer (PC) denoted?
%rsp, %rbp, %rip
Address: 0x804 | 0X808 | 0x80c | 0x810
Value: 0xCA | 0xFD | 0X12 | 0x1E
You’ve been given operands:
a) %rcx
b) (%rax)
c) $0x808
d) 0x808
e) 0x8(%rax)
What are their forms, translation and values?
Register: %rax | %rbx | %rcx |%rdx
Value: 0x804 | 0x10 | 0x4 | 0x1
Forms are registers, memory or constant.
form | translation | value
a) register | %rcx | 0x4
b) memory | M[%rax] or M[0x804] | 0xCA
c) constant | 0x808 | 0x808
d) memory | M[0x808] | 0xFD
e) memory | M[%rax+8] or M[0x80c] | 0x12
Address: 0x804 | 0X808 | 0x80c | 0x810
Value: 0xCA | 0xFD | 0X12 | 0x1E
You’ve been given operands:
a) (%rax, %rcx)
b) 0x4 (%rax, %rcx)
c) 0x800 (%rdx,4)
d) (%rax, %rdx, 8)
What are their forms, translation and values?
Register: %rax | %rbx | %rcx |%rdx
Value: 0x804 | 0x10 | 0x4 | 0x1
form | translation | value
a) memory | M[%rax +%rcx] or M[0X808] | 0xFD
b) memory | M[%rax+%rcx+4] or M[0X80c] | 0x12
c) memory | M[0x800 + %rdx x 4] or M[0x804]| 0xCA
d) memory | M[%rax + %rdx x 8] or M[0x80c] | 0x12
Translate these instructions:
a) lea 8 (%rax), %rax
b) lea (%rax, %rdx), %rax
c) lea (%rax, 4), %rax
d) lea -0x8(%rcx), %rax
e) lea -0x4(%rcx, %rdx, 2), %rax
translation | value
a) 8 + %rax -> %rax | 13 -> %rax
b) %rax + %rdx -> %rax | 9 -> %rax
c) %rax x 4 -> %rax | 20 -> %rax
d) %rcx - 8 -> %rax
e) %rcx+%rdx x 2 - 4 -> %rax
values are arbitrary to provide the sintax for writing
Difference between MIPS and ARM?
MIPS has a fixed length of 32-bit instruction format, 32 general purpose registers, only load and store can access memory, has delay slot
ARM has variable length (16/32/64 bits), 16 or 32 registers, no delay slot
What does ISA consist of?
Registers, address and data buses + the instruction set
What design issues are there to consider?
Number of explicit operands: 0, 1, 2 or 3
Location of operands: registers, accumulator, memory
Specification of operand location: addressing modes, size, supported operations
How would you write 1-address instruction that is accumulator based?
ADD X
i’ll be really fucking honest, idek if this is the right question.
ADD X -> ACC = ACC + Mem[X]
If we say ADD R1, we add this value to accumulator and store it there.
How would you write ADD, 0-address instructions stack-based?
ADD->TOS=TOS+NEXT
1st 2 elements would be taken out, added, then their sum is put on stack
Write ADD A, B that is memory-memory based?
ADD A,B -> Mem[A]=Mem[A]+Mem[B]
ADD A,B,C - Mem[A]=Mem[B]+Mem[C]
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Write LOAD R1,X register-memory based
LOAD R1,X - R1=Mem[X]
What does an instruction consist of?
Opcode and operand(s)
What can source and destination operand be specified as?
source
immediate data, ( ADD R1, #10)
naming a register
address (ADD R1, LOC A)
destination
register
memory address
