Week 7 & 9 - ISA + Assembly

Question 1

What is ISA?

Answer 1

set of instructions and binary encodings of machine-level programs

Interface between software and hardware.

Question 2

How are different types of operands written?

constant, register, memory

Answer 2

constant - preceded by the $ sign
register - mov %rsp, %rbp
memory - mpv -0x4(%rbp), %eax

$ox2 is literally hex ox2
(r) substract 0x4 from %rbp and then m. lookup

Question 3

How are stack pointer register, frame pointer register (base pointer) and instruction pointer (PC) denoted?

Answer 3

%rsp, %rbp, %rip

Question 4

Address: 0x804 | 0X808 | 0x80c | 0x810
Value: 0xCA | 0xFD | 0X12 | 0x1E

You’ve been given operands:
a) %rcx
b) (%rax)
c) $0x808
d) 0x808
e) 0x8(%rax)
What are their forms, translation and values?

Register: %rax | %rbx | %rcx |%rdx
Value: 0x804 | 0x10 | 0x4 | 0x1

Forms are registers, memory or constant.

Answer 4

form | translation | value
a) register | %rcx | 0x4
b) memory | M[%rax] or M[0x804] | 0xCA
c) constant | 0x808 | 0x808
d) memory | M[0x808] | 0xFD
e) memory | M[%rax+8] or M[0x80c] | 0x12

Question 5

Address: 0x804 | 0X808 | 0x80c | 0x810
Value: 0xCA | 0xFD | 0X12 | 0x1E

You’ve been given operands:
a) (%rax, %rcx)
b) 0x4 (%rax, %rcx)
c) 0x800 (%rdx,4)
d) (%rax, %rdx, 8)
What are their forms, translation and values?

Register: %rax | %rbx | %rcx |%rdx
Value: 0x804 | 0x10 | 0x4 | 0x1

Answer 5

form | translation | value
a) memory | M[%rax +%rcx] or M[0X808] | 0xFD
b) memory | M[%rax+%rcx+4] or M[0X80c] | 0x12
c) memory | M[0x800 + %rdx x 4] or M[0x804]| 0xCA
d) memory | M[%rax + %rdx x 8] or M[0x80c] | 0x12

Question 6

Translate these instructions:
a) lea 8 (%rax), %rax
b) lea (%rax, %rdx), %rax
c) lea (%rax, 4), %rax
d) lea -0x8(%rcx), %rax
e) lea -0x4(%rcx, %rdx, 2), %rax

Answer 6

translation | value
a) 8 + %rax -> %rax | 13 -> %rax
b) %rax + %rdx -> %rax | 9 -> %rax
c) %rax x 4 -> %rax | 20 -> %rax
d) %rcx - 8 -> %rax
e) %rcx+%rdx x 2 - 4 -> %rax

values are arbitrary to provide the sintax for writing

Question 7

Difference between MIPS and ARM?

Answer 7

MIPS has a fixed length of 32-bit instruction format, 32 general purpose registers, only load and store can access memory, has delay slot
ARM has variable length (16/32/64 bits), 16 or 32 registers, no delay slot

Question 8

What does ISA consist of?

Answer 8

Registers, address and data buses + the instruction set

Question 9

What design issues are there to consider?

Answer 9

Number of explicit operands: 0, 1, 2 or 3
Location of operands: registers, accumulator, memory
Specification of operand location: addressing modes, size, supported operations

Question 10

How would you write 1-address instruction that is accumulator based?
ADD X

i’ll be really fucking honest, idek if this is the right question.

Answer 10

ADD X -> ACC = ACC + Mem[X]

If we say ADD R1, we add this value to accumulator and store it there.

Question 11

How would you write ADD, 0-address instructions stack-based?

Answer 11

ADD->TOS=TOS+NEXT

1st 2 elements would be taken out, added, then their sum is put on stack

Question 12

Write ADD A, B that is memory-memory based?

Answer 12

ADD A,B -> Mem[A]=Mem[A]+Mem[B]
ADD A,B,C - Mem[A]=Mem[B]+Mem[C]

aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

Question 13

Write LOAD R1,X register-memory based

Answer 13

LOAD R1,X - R1=Mem[X]

Question 14

What does an instruction consist of?

Answer 14

Opcode and operand(s)

Question 15

What can source and destination operand be specified as?

Answer 15

source
immediate data, ( ADD R1, #10)
naming a register
address (ADD R1, LOC A)
destination
register
memory address

Question 16

Name addressing modes?

Answer 16

immediate, direct, indirect, register, register indirect, relative, indexed, stack, autoincremenet, autodecrement.

Question 17

Name instruction formats?

Answer 17

implied (NOP, HALT),
1-address (ADD X, LOAD M),
2-address (ADD X,Y),
register-memory (ADD R1, X),
register-register (ADD, R1,R2,R3)

Question 18

opcode | reg. dest | reg. src | data
LOAD | 01011 | 00010 | 0000000001100100
What is this translated?

Answer 18

LOAD R11, 100(R2)
R11 = Mem(R2+100)

Question 19

opcode | reg. dest | reg. src | reg src. | ALU function

ALU op | 01011 | 00101 | 01000 | ADD
What is this translated?

Answer 19

ADD R2, R5, R8
R2=R5+R8

Question 20

What do addressing modes specify?

Answer 20

They specify the mechanism by which the operand data can be located.

Question 21

Explain immediate addressing.

Answer 21

No memory reference, fast but limited range, operand is part of the instruction itself.

ADD #25 (ACC = ACC+25)
ADD R1,R2,42 (R1=R2+42)

opcode+immediate data

Question 22

Explain direct addressing.

Answer 22

holds memory address, limited address space.

ADD R1, 20A6H
R1=R1+Mem[20A6H]

opcode+operand address

Question 23

Explain indirect addressing.

Answer 23

Field holds the memory address which holds ANOTHER memory address.
It requires TWO memory accesses.
Slower, but large address space, not limited bu the number of bits in operand address like direct addressing.

ADD R1, (LOC A)
(in LOC A is LOC B, in LOC B is 10)
ADD R1, (20A6H) // R1=R1+(Mem[20A6])

Question 24

Explain register addressing.

Answer 24

The operand is held in REGISTER, few bits needed.

ADD R1, R2, R3 // R1=R2+R3
MOV R2, R5 // R2 = R5

Question 25

Explain indirect addressing.

Answer 25

Specifies a REGISTER which holds the MEMORY ADDRESS. ADD R1, (R5) // PC = R1+Mem[R5]

Question 26

Explain relative addressing (PC relative).

Answer 26

Specifies an offset of displacement, which is added to the program counter (PC) to get the effective address of the operand. opcode + offset.

Question 27

Explain the indexed addressing.

Answer 27

LOAD R1, 1050 (R3) // R3 = Mem[1050+R3] Offset gives the starting address of the array and the index register value specifies the array element to be used.

Question 28

Explain the stack addressing.

Answer 28

Operand is implicitly on top of the stack. Examples ADD, PUSH X, POP X. PUSH, POP, CALL , RET instructions automatically modify SP (Stack Pointer).

Question 29

Consider the following memory values and a one-address machine with an accumulator, what values do the following instructions load into accumulator? Word 20 contains 40 Word 30 contains 50 Word 40 contains 60 Word 50 contains 70 Do this for these 3: 1. Load immediate 20 2. Load direct 20 3. Load indirect 20

Answer 29

Word 20 contains 40 Word 30 contains 50 Word 40 contains 60 Word 50 contains 70 1) **Load immediate 20** ACC <- 20 2) **Load direct 20** ACC <- Mem[20] ACC <- 40 3) **Load indirect 20** ACC <- Mem[Mem[20]] ACC <- Mem[40] ACC <- 60

Question 30

Consider the following memory values and a one-address machine with an accumulator, what values do the following instructions load into accumulator? Word 20 contains 40 Word 30 contains 50 Word 40 contains 60 Word 50 contains 70 Do this for these 3: 1. Load immediate 30 2. Load direct 30 3. Load indirect 30

Answer 30

Word 20 contains 40 Word 30 contains 50 Word 40 contains 60 Word 50 contains 70 1) **Load immediate 30** ACC <- 30 2) **Load direct 30** ACC <- Mem[30] ACC <- 50 3) **Load indirect 30** ACC <- Mem[Mem[30]] ACC <- Mem[50] ACC <- 70

Question 31

How many cycles do we need for ADD A[R0], @B 3, 4, 5, or 6?

Answer 31

We need ONE memory access for A[R0] (index addressing), and TWO memory accesses for @B (indirect addressing), and ONE for ADD instruction. That is 4 memory acceses/reads.

Question 32

The memory locations 1000, 1001, and 1020 have data values 18, 1 and 16 respectively before the following program is executed. MOV Rs, 1 LOAD Rd, 1000(Rs) ADD Rd, 1000 STORE O(Rd), 20 a) Memory location 1000 has value 20 b) Memory location 1020 has value 20 c) Memory location 1021 has value 20 d) Memory location 1001 has value 20

Answer 32

**MOV Rs, 1** Rs = 1 **LOAD Rd, 1000(Rs)** Rd = Mem[1001]; Rd=1 **ADD Rd, 1000** Rd=1001 **STORE O(Rd), 20** Mem[0+1001] = 20 d) Memory location **1001** has value 20