Week 4 - Internal Memory & Digital Logic

Question 1

Name 5 components of von Neumann Architecture

Answer 1

processing unit, control unit, memory unit, input unit(s), output unit(s)

1. The processing unit executes program instructions.
2. The control unit drives program instruction execution on the processing unit. Together, the processing and control units make up the CPU.
3. The memory unit stores program data and instructions.
4. The input unit(s) load program data and instructions on the computer and initiate program execution.
5. The output unit(s) store or receive program results.

Question 2

What is a bus?

Answer 2

a communication chanel that transfers binary values between communication endpoints

Buses connect the units, and are used by the units to send control and data information to one another. he units use the control bus to send control signals that request or notify other units of actions, the address bus to send the memory address of a read or write request to the memory unit, and the data bus to transfer data between units.

Question 3

Difference between Hardvard and von Neumann Architecture?

Answer 3

In the Harvard architecture, data and instructions have separate memory spaces, enabling simultaneous access to both. In contrast, the Von Neumann architecture uses a single memory space for both data and instructions, fetching and executing them sequentially.

Question 4

Which units together make up the CPU?

Answer 4

control and processing unit

Question 5

What is processing unit composed of?

Answer 5

ALU (arithmetic/logic unit) and a set of registers

Question 6

What is a register?

Answer 6

A register is a small, fast unit of storage used to hold program data and the instructions that are being executed by the ALU.

Each register is capable of holding one data word.

Question 7

What does the control unit do?

Answer 7

The control unit drives the execution of program instructions by loading them from memory and feeding instruction operands and operations through the processing unit.

Question 8

What registers are there?

Answer 8

PC, IR, MAR, MDR, SP, ACC

Program Counter - memory address of the next instruction
Instruction Register - stores the current instruction 4
Memory Address Register - memory address of data
Memory Data Register - data currently accessed
Stack Pointer - memory address of the last item placed on stack
Accumulator - holds the result of computations

Question 9

What is word size?

(generally, but also for 8-bit, 16-bit, 32-bit, 64-bit architecture)

Answer 9

Word size is the number of bits of the standard data size that a processor handles as a single unit.

8, 18, 32, 64 bits

Question 10

What are input and output units (I/O)?

Answer 10

Output units refer to devices that retrieve and display information stored in memory, such as monitors or printers. Input units are devices that allow users to input data into memory, like keyboards or mice.

The input unit consists of the set of devices that enable a user or program to get data from the outside world into the computer. The most common forms of input devices today are the keyboard and mouse. Cameras and microphones are other examples.

The output unit consists of the set of devices that relay results of computation from the computer back to the outside world or that store results outside internal memory. For example, the monitor is a common output device. Other output devices include speakers and haptics.

Question 11

Explain the process of a von Neumann Machine executing a program.

Answer 11

fetch-decode-execute-store

1. The control unit fetches the next instruction from memory, takes it from PC and places it on the address bus and places a ‘read’ command on the control bus. The memory unit then reads it and sends the bytes stored at that address on the data bus. IR stores the bytes of the instruction received and the control unit increments the PC’s value.
2. The control unit decodes the instruction stored in IR. It then fetches data operand values from their lcoations, as input to the processing unit.
3. The processing unit executes the instruction. The ALU performs the instruction operation on instruction data operands.
4. The control unit stores the result to memory. Places the result on data bus, address of the storage location on the address bus and a ‘write’ command on the control bus. When received, memory unit writes the value to memory at the address.
   The I/O units are not directly involed in the execution of program instructions, they load program’s instructions and data and store or display the results.

Question 12

Name categories of circuit building blocks:

Answer 12

arithmetic/logic, control and storage circuits

Question 13

Draw an equality circuit:

Answer 13

https://diveintosystems.org/book/C5-Arch/_images/1biteq.png

Question 14

Draw an 1-bit Adder circuit:

Answer 14

https://diveintosystems.org/book/C5-Arch/_images/1bitadder.png

Question 15

Attempt at drawing a 1 bit 2-way MUX:

Answer 15

https://diveintosystems.org/book/C5-Arch/_images/1bitmux.png

Truth table is A,B,S then out is (BBBBAAAA)

Question 16

ATTEMPT at drawing a 1 bit 4-way MUX

personally i wouldn’t bother, but you do you

Answer 16

https://diveintosystems.org/book/C5-Arch/_images/nwaymux.png

Question 17

Write down the table for a two-way 1-bit demultiplexer, and a 2-bit decoder, along with their truth tables.

Answer 17

https://diveintosystems.org/book/C5-Arch/_images/dmuxdecoder.png

Question 18

Draw the computer memory hierarchy:

Answer 18

Genuinely believe this question will be skipped, you KNOW this

CPU, L1/2 cache, main memory, disk storage

Question 19

Downsides of von Neumann architecture:

Answer 19

Program can be written to view itself as data, thus enabling a self-modifying program. Also, if an instruction calls for (reading/writing) data from memory, the next instruction cannot be read from memory over the same bus until the current instruction has completed the data transfer (von Neumann bottleneck).

VNB is solved by the Hardvard architecture, but it’s far more expensive.

Question 20

What is a hit?

Answer 20

the requested data is found in a given level of memory

Question 21

What is a miss?

Answer 21

the requested data is not found in the given level of memory

Question 22

What’s a hit rate?

Answer 22

the requested data is not found in the given level of memory

Question 23

What’s a miss rate?

Answer 23

the percentage of memory accesses not found in a given level of memory.
Miss Rate = 1 - Hit Rate

Question 24

What’s a hit time?

Answer 24

the time required to access the requested information in a given level
of memory.

Question 25

What’s a miss penalty?

Answer 25

the time required to process a miss

Why it takes longer:
Replacing a block in an upper level of memory,
Additional time to deliver the requested data to the CPU
Significantly larger than the time to process a hit

Question 26

What is temporal locality?

Answer 26

Programs tend to access the same data repeatedly over time. If a program has used a variable recently, it is likely to use that variable again soon

Question 27

What is spatial locality?

Answer 27

accesses clustered in the address space (e.g. as in arrays, or loops): programs tend to access data that is nearby to the other previously accessed data.

If a program accesses data at N and N+4, it is likely to access N+8 soon

Question 28

What is capacity?

obviously in reference to this course

Answer 28

The amount of data a device can store.

Measured in bytes.

Question 29

What is latency?

Answer 29

the amount of time it takes for a device to respond with data after it has been
instructed to perform a data retrieval task

Measured in fractions of a second (ms, ns) or CPU cycles.

Question 30

What is transfer rate?

Answer 30

the amount of data that can be moved between the device and main memory
over some period of time, also known as throughput

Measured in bytes per second.

Question 31

Name arithmetic/logic circuits:

Answer 31

equality circuit, adders

Question 32

Name control circuits:

Answer 32

MUX, DEMUX, decoder

Question 33

Name storage circuits:

Answer 33

latches, flip flops

Question 34

What are edge and level triggered circuits?

Answer 34

• Edge triggered circuit: allowed to change state on either the rising or falling edge of the clock signal
• Level triggered: allowed to change state whenever the clock signal is either high or low.

Feedback: to remember a past state -> the output of a circuit is fed back as an input to the same circuit

Question 35

(S,R)->(0,0)
(S,R)->(1,0)
(S,R)->(0,1)
(S,R)->(1,1)

whatever this is? SR Flip Flop (draw it and the characteristic table?)

Answer 35

(S,R)->(0,0): keep current state
(S,R)->(1,0): Set (Q=1)
(S,R)->(0,1): Reset (Q=0)
(S,R)->(1,1): not allowed

Question 36

D Flip-Flop

give me inputs, type triggered, how many bits it stores?

Answer 36

2 inputs are data (D) and clock (C), it’s a positive edge-triggered flip-flop, used to store a single bit, the value oonly changes at the rising edge of a clock cycle.

Question 37

How many AND gates does an
n x 2^n decoder require? How many for 2 decoders?

such a random ass question

Answer 37

2^n, 2 x 2^(n/2)

Question 38

Combinational circuits lore?

Answer 38

A combinational logic circuit has output that depends only on the inputs given at any specific time and not on any previous inputs.
Combinational circuits are memoryless.

- Adders
- Decoders
- Multiplexers
- Programmable logic devices

Question 39

Sequential circuits are?

Answer 39

Sequential circuit has outputs that depend on previous and current inputs
They have the storage element (to remember previous outputs) and clocks as a way to order events.

- Flip flops
- Latches

Clock = circuit that emits a series of pulses of precise width and interval between consecutive pulses
Interval between consecutive pulses = clock cycle time
(1 - x100 MHz)
Clock speed measured in MHz, mills pulses per second

Question 40

How many external connections requires 8x4 memory chip?

Answer 40

3 for addressing, 4 for data links, 1 for power supply, 2 for control signals (chip selection and read/write).

11 external connections