Week 5 Flashcards

1
Q

What are the steps of the Fetch Decode Execute cycle?

A

Fetch - read an instruction from memory

Decode - identify the instruction

Execute - carry out the instruction

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2
Q

What is a Pipelined Cycle?

A

An ideal scenario, the rate of instruction execution is multiplied by the number of stages

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3
Q

What is Clock Cycle Time?

A

Time which each pipeline stage must complete its operation

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4
Q

What is Clock Speed?

A

Frequency at which the CPU’s clock runs (1/clock cycle time)

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5
Q

What is Execution Time (hint: … X … )?

A

Clock cycles for program x Clock cycle time

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6
Q

What are the 2 Pipeline Hazards?

A

Control Hazards

Data Hazards

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7
Q

What is a control hazard?

A

Occurs when a branch instruction changes the next instruction

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8
Q

What are the 3 ways to deal with control hazards?

A
  1. Stall the pipeline
  2. Assume branch not taken
  3. Branch prediction
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9
Q

What is Stalling the pipeline?

A

Stop fetching and executing next instructions until the branch result becomes known

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10
Q

What are the pros and cons of Stalling the pipeline?

A

Pros:

No need to do anything

Cons:

Wasting time and resources

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11
Q

What is Assuming the branch not taken?

A

The processor assumes branch not taken

Squashing instructions if wrong

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12
Q

What are the pros and cons of Assuming the branch not taken

A

Pros:

No need to guess the next instruction

Cons:

Wasting time and resources if branch taken

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13
Q

What is Branch Prediction?

A

The processor may try branch prediction based on past branches

If prediction is incorrect, instructions are squashed

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14
Q

What are the pros and cons of Branch Prediction?

A

Pros:

Can reduce wasted clock cycles

Cons:

Branch prediction overhead

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15
Q

What is a Data Hazard?

A

Occurs when an instruction requires a result from a previous instruction before that result has been computed/written

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16
Q

What are the types of Data Hazards?

A

Read after write (RAW) - True Dependency

Write after read (WAR) - Anti-dependency

Write after write (WAW) - Output dependency

17
Q

What is Read After write (RAW) - True Dependency?

A

Instruction writes, then another reads same location

Hazard if read happens before write completes

18
Q

What is Write After Read (WAR) - Anti-dependancy?

A

Instruction reads, followed by another writing to same location

Hazard if write completes before the read

19
Q

What is Write After Write (WAW) - Output Dependancy?

A

Two instructions write to same location

Hazard if writes occur in reverse intended order

20
Q

What are the side effects of Deeper Pipelines?

A

More pipeline stages means

A larger penalty for incorrect branch predictions

A bigger risk of data hazards

21
Q

What is Caching?

A

A processor fetches instructions and data from cache memory if possible

22
Q

What is Pipelining?

A

The execution of an instruction is divided into multiple stages

23
Q

What is a Branch Prediction?

A

A processor predicts branches based on past history, and squashes instructions if wrong

24
Q

What is Speculative Execution?

A

An optimization technique in which a processor (CPU) performs a series of tasks before it is prompted to, in order to have the information ready if it is required at any point

25
Q

What is Spectre and Meltdown?

A

Spectre and Meltdown are security vulnerabilities that affect modern computer processors. Discovered in early 2018, they exploit critical vulnerabilities in modern processors to potentially access sensitive data

26
Q

What is Spectre?

A

Vulnerability that affects modern computer processors

Unfortunate combo of:

Branch prediction

Speculative execution

Cache exploit of temporal locality

27
Q

What are the similarity and differences of Spectre and Meltdown?

A

Similarities:

Exploit built-in vulnerabilities, not bugs

Require attacker to be using the system

Differences:

Spectre reads memory from other processes

Meltdown can also read kernel memory from user space