Week 3

Question 1

Intel 8086 MPU

Answer 1

The DNA of the chip (x86 architecture) is likely at the centre of every computer

Question 2

8086 Architecture block diagram

Answer 2

The 8086 has a 2-stage pipeline so was designed to have 2 units: BIU and EU.

Process of “fetching next instruction while executing next instruction”

Question 3

Bus interface unit (BIU)

Answer 3

BIU communicates with external devices and peripherals including memory via the bus.

The left x block has something to do with memory segmentation.

The right side of the BIU has a buffer of queue to keep the BIU ahead of the EU which is 6 bytes long.

It generates 20-bit physical address for memory access
It fetches intructions from the memory
It transfers data to and from memory and I/O
Maintains the 6 byte prefetch instruction queue

Question 4

What is memory segmentation?

Answer 4

An OS memory management technique dividing a computer’s primary memory into segments.

For 8086 memory is divided into 4 segments:
-Code segment
-Stack segment
-Data segment
-Extra segment

Each of these are 16 bits which add up to 64 bits in total

Question 5

Code segment

Answer 5

Stores programs
Instructions are fetched from the code segment
It operates in “first come first serve”

Question 6

Stack segment

Answer 6

Stores stacks
Operates in “last in first out” manner (like checking emails)

Question 7

Data segment and extra segment

Answer 7

store general data

Question 8

Why do we need memory segmentation?

Answer 8

-Segmentation helps to organise memory and prevent accidental overrides
-More important to work with 8086 address bus efficiently

Question 9

Segmented memory addressing

Answer 9

-Width of address bus in 8086 is 20
-The 20-bit unique address is called physical address which is the real address
-20 bits is 2.5 bytes which is not byte compatible and is inconvenient to work with
- A virtual model of the address is created which consists of a 16-bit segment address and 16-bit offset address
- For memory access, the memory management unit (x block in x86 architecture) uses virtual addresses to generate 20 bit physical address

Question 10

What are the two memory units in an 8086 microprocessor and whats their function?

Answer 10

BIU: bus interface unit does fetch
EU: execution unit does execute

The 8086 microprocessor has a 2 stage pipeline

Question 11

What are the two virtual addresses used to generate 20 bit physical address?

Answer 11

-These are a 16-bit segment address and 16-bit offset address

• Segment address: gives the starting address of the segment and indicates where the segment is
• Offset address: indicates where the target memory cell is

Question 12

What’s the physical address formula in terms of virtual addresses?

Answer 12

PA = (Segment x 10H) + Offset

Question 13

Example for physical address formula

Answer 13

Segment address = 1234H
offset address = 0011H

PA = segment x 10H x offset
PA = 1234H x 10H x 0011H
PA = 12340H + 0011H
PA = 12351H

Question 14

What’s the max size of a segment?

Answer 14

It is 64KB
This is because of the offset address being 16 bits
2^16 = 64KB

Programmers can create multiple code/stacks/data segments until the entire 1MB is used but only one of each type will be currently active. You can’t work on two segments simultaneously.

Question 15

What are the segment address and offset registers for all 4 segments?

Answer 15

Code Segment:
Segment is CS (code segment)
Offset is IP (instruction pointer)

Stack Segment:
Segment is SS (stack segment)
Offset is SP/BP (stack/base pointer)

Data Segment:
Segment is DS (data segment)
Offset is SI (source index)

Extra Segment:
Segment is ES (extra segment)
Offset is DI (destination index)

Offset registers point to specific memory locations under each segment

Question 16

Memory segmentation vs segment registers

Answer 16

They are the same thing but segment registers store addresses of segments.

Question 17

Memory segmentation vs memory banking

Answer 17

-Both deal with memory
-Memory segmentation is a method to manage memory and doesn’t make a change to the memory chip
-Memory banking physically divides the memory into separate chips to allow access to multiple memory cells at a time

Question 18

What is the EU?

Answer 18

The main components of the EU are General purpose registers, the ALU, offset registers, the Instruction Register and Instruction Decoder, and the Flag/Status Register.

Execution unit instruct the BIU from where to fetch the data/instructions
It also decodes and executes

Question 19

Instructions: BIU to EU

Answer 19

-Instructions come from queue in BIU
-The instructions are in binary form and are called Opcodes
-The Opcodes go into the control unit which decodes the opcode and releases control signals
-The control signals go to the ALU and the registers

Question 20

6 byte Pre-fetch queue

Answer 20

The prefetch unit allows the 8086 to perform multiple instruction fetches in parallel.

• First come first serve
• Fetches next instruction by BIU from CS while ex3ecuting the current instruction is called pipelining
• 6 bytes because max size of instructions in 8086 is 6 bytes

Question 21

What’s the execution process of the whole 8086 architecture?

Answer 21

1. All instructions are stored in memory hence to fetch any instruction first task is to obtain the Physical address of the instruction is to be fetched. This task is done by BIU and Segment Registers. Suppose the Code segment has a Segment address and the Instruction pointer has some offset address then the physical address calculator circuit calculates the physical address in which our instruction is to be fetched using the formula.
2. After the address calculation instruction is fetched from memory and it passes through Data bus, the instruction pre-fetch queue fills up. Each byte will take up one of the 6 bytes.
3. When our instruction is ready for execution, according to the FIFO property of the queue instruction comes into the control system in the EU. Here instruction decoding takes place. The decoding control system generates an opcode that tells the microprocessor unit which operation is to be performed. So the control system sends signals all over the microprocessor about what to perform and what to extract from General and offset Registers.
4. After decoding microprocessor fetches data from GPR and according to instructions like ADD, SUB, MUL, and DIV data residing in GPRs are fetched and put as ALU’s input. and after that addition, multiplication, division, or subtraction whichever calculation is to be carried out. According to arithmetic, flag register values change dynamically.
5. While Instruction was decoding and executing from step-3 of our algorithm, the Bus interface Unit doesn’t remain idle. it continuously fetches an instruction from memory and put it in a pre-fetch queue and gets ready for execution in a FIFO manner whenever the time arrives.
6. Here the fetch, decode, and execution process happens in parallel and not sequentially. This is called pipelining, and because of the instruction pre-fetch queue, all fetching, decoding, and execution process happen side-by-side. Hence there is partitioning in 8086 architecture like Bus Interface Unit and Execution Unit to support Pipelining phenomena.

Question 22

General purpose registers

Answer 22

8086 has four 16-bit general purpose registers AX, BX, CX, and DX which store intermediate values during execution. Each of these has two 8-bit parts (higher and lower).

AX: It holds operands and results during multiplication and division operations.

BX: It holds the offset address in indirect addressing modes.

CX: It holds the count for instructions like a loop, rotates, shifts and string operations.

DX: It is used with AX to hold 32-bit values during multiplication and division.

Question 23

What is assembly Language

Answer 23

Low Level:
-Deals directly with internal structure of the CPU
-In contrast to high level programming languages

Machine Specific:
- example is x86 is a programming language for the x86 class of processors

Question 24

Why is assembly used

Answer 24

• Has complete control over a systems resources
• Direct access to hardware
• Better understanding of architecture issues
• Improve algorithm development skills

Assembly language is the more than low level and less than high-level language so it is intermediary language. Assembly languages use numbers, symbols, and abbreviations instead of 0s and 1s.For example: For addition, subtraction and multiplications it uses symbols likes Add, sub and Mul.