Week 2 Flashcards
n-bit processors?
n-bit processor indicates it has an n-bit ALU. The ALU decides how much data can be processed at a time. A 16-bit ALU can process 16 bits of data at a time
Data Bus
-Transfers data
-Width determines how much data can be transferred at a time in one cycle
-The wider the data bus, the more data can be transferred in one cycle so less number of cycles required and a faster processor.
Control Bus
-Carries control signals
-Control signals include:
-Selection of memory or I/O devices
-Direction of data transfer
-Synchronisation of data transfer
Address Bus
Address bus transfers data .
1 wire can address 2 locations.
Intel 8086 has a 20-bit address bus so can address 2^20 locations
How many bits in one byte
8 bits in one byte
One memory location stores on byte of data
2^N locations can store 2^N bytes of data
How is data “2023H” stored in memory?
Its stored as 2 bytes. Instead of one 2023H being stored as one, a 20H and a 23H is stored separately. One memory cell can store 8 bits maximum.
Whats the little endian rule?
Its a type of addressing that refers to the order of data stored in memory.
The LSB is first stored and subsequent bits are stored incrementally.
In other words, the lower byte of data are stored at the lower byte of memory
To transfer the data 2023H to memory using 16 bit data bus…?
2 memory locations need to be accessed. In one cycle, 2 addresses can be transferred by the address bus. Therefore we need 2 cycles to transfer 2023H
What is memory banking? (16 bit 8086)
Goal is to access two consecutive memory locations in one cycle (16 bits). The memory chip is equally divided into banks. Minimum byte operation needs 1 byte so 8 bits so 2 are needed for 16 bits.
Transferring data using even bank and odd bank
The two banks are even and odd. The even bank is the lower bank and the odd bank is the higher bank. Now 2 memory locations can be accessed at the same time. Each bank is connected to the processor using a tablet, using 8 wires tied together and 16 bit database. So 16 bits of data can be transferred at the same time.
Memory Banking? (32 bit 8086)
For 32 bit, four addresses need to be accessed simultaneously to obtain 32 bits of data at a time. So we need to divide the memory physically to four chip and then 32 bits can be accessed at the same time.
What is aligned/misaligned memory access?
A memory access is said to be aligned when the data being accessed is n-byte long and the datum address is n-byte aligned.
What are registers?
A temporary storage locations inside the CPU to store data/instructions/address.
Status/Flag registers
- Contains the current state of a CPU
- Checked by CPU before execution of every instruction
- Updated after every execution
- 8086 has a 16-bit flag register
- 1 bit per flag
- 7 bits unused
- 9 bit used: 6 status flags and 3 control flags
Flag purposes
- CF: carry flag is set to 1 if there is an unsigned overflow or if there is a borrow during subtraction out of the MSB
- PF: parity flag is set to 1 if result from ALU has even number of 1s
- AF: auxiliary flag is similar to CF but watches over the lower 4-bit
- ZF: zero flag is set to 1 if the result from the ALU is zero
- SF: signal flag copies to the MSB of the result from the ALU
- OF: overflow flag is set to 1 when the result is out of range/of signed operation
- TF: trap flag set to 1 to get into single step mode for debugging
- IF: interrupt flag set to 1/0 to enable/mask interrupts
- DF: flag set to 1/0 to set direction to decrementing/incrementing
What is pipelining?
Pipelining is a technique for implementing instruction-level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming instructions into a series of sequential steps performed by different processor units with different parts of instructions processed in parallel.
What are the types of interrupt:
Hardware interrupts:
- Asynchronous: not related to what code the processor is currently executing
Software interrupts:
- Synchronous: the result of specific instructions executing
8086 Interrupt service routine (ISR)
ISR is a subroutine which processor is forced to execute to respond to a specific event
- An interrupt signal is emitted
- CPU suspends its current work if interrupt is accepted and saves its status:
-It saves the instruction address for the processor to return later
- saves the flag registers
- resets two flags which are IF and TF
- loads the ISR address - CPU executes ISR:
- An ISR is a specifically written program to service an interrupt
- For each interrupt INTn, there’s an interrupt service routine ISRn
- In 8086, there’s 256 interrupt. The addresses are stored in the IVT - After the CPU returns to the main program and continue what it was doing
- IRET instruction
- Restores instruction address
- Restores flag register values
8086 Interrupt vector table (IVT)
- IVT stores the address of the ISRs
- They’re stored at fixed addresses of the memory
- For example for intel 8086 the first 1kb of memory is reserved for the IVT
- There’s max 256 interrupts
- Each interrupt requires 4 memory locations to store the ISR address
8086 Interrupt sources
- Hardware interrupts
- Software interrupts
- Internally generated interrupts
Interrupt - Masking
We can enable and disable most hardware interrupts as needed. Non-maskable hardware interrupt has priority over maskeable interrupts
Interrupt - Vectored/Non-vectored
If a hardware interrupt has a fixed vector address, its a vectored interrupt otherwise its a non vectored interrupt
Interrupt - controller
Multiplexes has a number of possible interrupt sources on the platform for presentation to the processor. Can be integrated part in microcontrollers
Interrupt - Priority
Exceptions and software interrupts have higher priority
Adjustable hardware interrupt priorities in modern processors
Always consider priority and check processor manuals
Interrupts - Nested system
These are interrupts allowed at anytime and anywhere even when an ISR is being executed
Interrupts are served according to priority
Opposite to nested interrupts: sequential interrupts
