Week 2: Clocked Flip Flop

Question 1

D Flip Flop

Answer 1

A D Flip Flop is a clocked Flip Flop that, on a given clock pulse (either rising or falling edge, depending on its configuration) stores the value at the input D.

Question 2

JK Flip Flop

Answer 2

A programmable gate clocked flip flop which can mimic what the behaviours of a T, D and RS flip flop.

The behaviour of the gate is determined by the values of J & K

Question 3

T Flip Flops

Answer 3

A T Flop Flop is a toggle flip flop. When the input is set high, the state of the flip flop toggles on each clock pulse. When the input is pulled low, the flip flop retains its current state, and does not change.

Question 4

J0 & K0

Answer 4

No change to the output Q

Question 5

J0 & K1

Answer 5

Q’ = 1 (Reset)
When Q = 0, K is deactivated.

J and K can be used exactly as the Set and Reset inputs in an R-S Flip Flop, but without the issue of instability.

Question 6

J1 & K0

Answer 6

Q = 1 (Set)
When Q’ = 0, J is deactivated.

J and K can be used exactly as the Set and Reset inputs in an R-S Flip Flop, but without the issue of instability.

Question 7

J1 & K1

Answer 7

Toggle

If J and K are both set high, then the Flip Flop behaves as a T Flip Flop, and changes its state on each clock pulse.