Week 1

Question 1

A program is made of a series of what?

Answer 1

Instructions

Question 2

A program’s instructions are stored where?

Answer 2

In the Program Memory

Question 3

What register specifies the address of the next instruction to be executed?

Answer 3

The Program Counter (PC) register

Question 4

What is the purpose of the Control Logic in the CPU block diagram?

Answer 4

To decode the instructions and use the resulting information to control other subsystems

Question 5

What is the purpose of the Link Register (LR) ?

Answer 5

To store the return address when a branch and link instruction is used

Question 6

What is it called when a CPU starts the next instruction before execution of the current instruction is completed ?
This is done to increase processing speed.

Answer 6

Pipelining

Question 7

What four aspects of a processor can Architecture define?

Answer 7

1) Programmer’s model
2) Instruction set architecture
3) Exception model
4) Debug architecture

Question 8

Cortex M0+ processors implement what type of architecture?

Answer 8

ARMv6-M

Question 9

The ARM programming model uses load/store architecture. What is meant by load/store architecture?

Answer 9

Data must be loaded into registers before processing and then optional stored back in memory afterwards. Data cannot be processed from memory directly.

Question 10

What are the two data types native to ARMv6-M?

Answer 10

Signed and unsigned 32-bit values.

Question 11

Can a CPU use non-native data types?

Answer 11

Yes, but emulating them may require more instructions and take more time.

Question 13

What is the purpose of the Stack Pointer (SP) register?

Answer 13

The stack pointer manages a data storage structure called the stack.

Question 14

What is the purpose of the Program Counter (PC) register?

Answer 14

To store the address of the next instruction to be executed.

Question 15

What is the purpose of the PRIMASK register?

Answer 15

The PRIMASK register will cause the CPU to ignore some types of exceptions if it is set to one.

Question 16

What is the purpose of the CONTROL register?

Answer 16

It determines which stack pointer is used if the processor is in thread mode.
It also determines if the processor should run in privileged or unprivileged level when in thread mode.

Question 17

The Program Status Register (PSR) has three ‘views’. What are they and what are their functions?

Answer 17

APSR - Shows the condition flag bits.
IPSR - Holds the current exception handler.
EPSR - Shows if the CPU is in Thumb mode.

Question 18

Define byte-addressable

Answer 18

When memory addresses specify a particular byte the memory is said to be byte addressable.

Question 19

ARMv6-M architecture has what size address space?

Answer 19

32-bit

Question 20

True or False
The address space is divided into various regions for different uses?

Answer 20

True

Question 21

In Little-Endian systems is the least or most significant bit stored in at the lowest address?

Answer 21

Least

Question 22

In Big-Endian systems is the least or most significant bit stored in at the lowest address?

Answer 22

Most

Question 23

In ARMv6-M systems are instructions stored as little or big endian?

Answer 23

Little but data can be either. In the Kinetis micro-controllers data is stored little endian.

Question 24

What software tool converts code from high level languages like C into assembly language?

Answer 24

A compiler.

Question 25

What is the name for the group of software programs that includes a compiler and and assembler?

Answer 25

Program build tool-chain.

Question 26

What does IDE stand for and what does it include (usually)?

Answer 26

Integrated Development Environment.
1) Program build tool-chain
2) Programmer
3) Debugger

Question 27

Name the three stages the CPU core performs to execute an instruction.

Answer 27

Fetch.
Decode.
Execute.

Question 28

What is the differene between von Neuman and Harvard architecture?

Answer 28

von Neuman: memory holds data and instructions so both share a bus
Harvard: Seperate memory for data and instructions, two busses.

Harvard is faster but more complex.

Question 29

Does the Cortext M0+ have harvard or von neuman architecture?

Answer 29

von Neuman

Question 30

What is the purpose of NVIC in the core?

Answer 30

The Nested Vector Interrupt Controller manages and prioritises incoming interrupts.