VLSI Presentation Flashcards
VLSI
Very large scale integrated circuits
Process
Sequence of steps that will be performed to fabricate the IC
Technology
The foundry process and the associated design rules
Process are often identified by
Trade name
Types of devices they can be used to make
Characteristic feature size
Trade name
ON semi’s C5 process
Device type
NMOS process
PMOS process
CMOS process
BiCMOS process
Feature size
14nm
350nm
Process node
Standardized series of process steps used to fabricate ICs
Terminology used when the process is labeled by its feature size
-Intel’s 32nm process node
Device half-pitch
Distance on the wafer between the feature on a transistor and the same feature on an adjacent transistor
CMOS process
NMOS
- p+ body, n+ source and drain
- p-type substrate
PMOS
-n+ body, p+ source and drain, n-well
Masks
Sent to foundry
Result of EDA flow
Set of masks of each of the process layers
Each of the colored design layers are different masks used separately as inputs to different steps of the process
Photolithography
Si, SiO2, Resist
Shine UV light source, creates mask, remove unprotected photo resist
Negative resist, positive resist, lift off (removes resist), etch back (removes SiO2)
Fabrication
- Grow field oxide
- Etch oxide for pMOSFET
- Diffuse n-well
- Grow gate oxide
- Deposit polysilicon
- Etch polysilicon and oxide
- Implant sources and drains
- Grow nitride
- Etch nitride
- Deposit metal
- Etch metal
Field oxide, gate oxide, polysilicon, nitride, metal
Electronic design automation (EDA)
Software-supported design procedure for turning circuit ideas or block diagrams into the layout files necessary for IC fabrications (PCB fabrication)
EDA steps
- Schematic capture
- Netlist extraction (from schematic)
- Basic simulation
- Schematic-driven layout
- Netlist extraction (from layout)
- LVS or NCC
- Parasitic extraction
- Final simulation
Schematic capture
Entering into the software all circuit schematics generated (after by hand)
Netlist extraction (from schematic)
Netlist generated from schematic
Spice engines simulate net-lists, not diagrams
Basic simulation
Simulate the extracted netlist with no information about physical arrangement
Schematic-driven layout
Using confirmed-functional schematic to decide where to put shapes on mask layers
Involves DRC
Design Rule Check (DRC)
Foundry provides design rules
Netlist extraction (from layout)
Really smart software looks over your layer masks to decide what circuit you’ve built
LVS (layout-vs-schematic) or NCC (network-consistency-check)
Compares the layout netlist and the schematic netlist
Parasitic extraction
Form of netlist extraction performed only on the layout
Included inferred capacitances from adjacent metal layers
Complex parasitic devices may exist (parasitic diodes, BJTs) which alter the behavior
Final simulation
Core circuit’s netlist is simulated with parasitics to determine if adjustments need to be made
Other ideas involved in EDA
Design-for-test
Design-for-manufacturing
This EDA design flow is how we achieve reliability and yield even though
VLSI circuits have many nodes
VLSI circuits tend to be mass-manufactured
VLSI circuit components are micro or nanoscopic
Thyristor
When of the transistors is turned on, the other one begins conducting too
The both keep each other in saturation until all the voltages in the system return to 0
Latch-up
Can only be detected in parasitic simulation
Causes a DC short between power and ground
Can be triggered by:
- noise in power supply
- cosmic rays
- transients from RLC circuits
Discovered during simulation, extra layers for isolation are added where needed or the transients are mitigated
