VLSI Presentation

Question 1

VLSI

Answer 1

Very large scale integrated circuits

Question 2

Process

Answer 2

Sequence of steps that will be performed to fabricate the IC

Question 3

Technology

Answer 3

The foundry process and the associated design rules

Question 4

Process are often identified by

Answer 4

Trade name

Types of devices they can be used to make

Characteristic feature size

Question 5

Trade name

Answer 5

ON semi’s C5 process

Question 6

Device type

Answer 6

NMOS process
PMOS process
CMOS process
BiCMOS process

Question 7

Feature size

Answer 7

14nm

350nm

Question 8

Process node

Answer 8

Standardized series of process steps used to fabricate ICs

Terminology used when the process is labeled by its feature size
-Intel’s 32nm process node

Question 9

Device half-pitch

Answer 9

Distance on the wafer between the feature on a transistor and the same feature on an adjacent transistor

Question 10

CMOS process

Answer 10

NMOS

• p+ body, n+ source and drain
• p-type substrate

PMOS
-n+ body, p+ source and drain, n-well

Question 11

Masks

Answer 11

Sent to foundry

Question 12

Result of EDA flow

Answer 12

Set of masks of each of the process layers

Each of the colored design layers are different masks used separately as inputs to different steps of the process

Question 13

Photolithography

Answer 13

Si, SiO2, Resist

Shine UV light source, creates mask, remove unprotected photo resist

Negative resist, positive resist, lift off (removes resist), etch back (removes SiO2)

Question 14

Fabrication

Answer 14

1. Grow field oxide
2. Etch oxide for pMOSFET
3. Diffuse n-well
4. Grow gate oxide
5. Deposit polysilicon
6. Etch polysilicon and oxide
7. Implant sources and drains
8. Grow nitride
9. Etch nitride
10. Deposit metal
11. Etch metal

Field oxide, gate oxide, polysilicon, nitride, metal

Question 15

Electronic design automation (EDA)

Answer 15

Software-supported design procedure for turning circuit ideas or block diagrams into the layout files necessary for IC fabrications (PCB fabrication)

Question 16

EDA steps

Answer 16

1. Schematic capture
2. Netlist extraction (from schematic)
3. Basic simulation
4. Schematic-driven layout
5. Netlist extraction (from layout)
6. LVS or NCC
7. Parasitic extraction
8. Final simulation

Question 17

Schematic capture

Answer 17

Entering into the software all circuit schematics generated (after by hand)

Question 18

Netlist extraction (from schematic)

Answer 18

Netlist generated from schematic

Spice engines simulate net-lists, not diagrams

Question 19

Basic simulation

Answer 19

Simulate the extracted netlist with no information about physical arrangement

Question 20

Schematic-driven layout

Answer 20

Using confirmed-functional schematic to decide where to put shapes on mask layers

Involves DRC

Question 21

Design Rule Check (DRC)

Answer 21

Foundry provides design rules

Question 22

Netlist extraction (from layout)

Answer 22

Really smart software looks over your layer masks to decide what circuit you’ve built

Question 23

LVS (layout-vs-schematic) or NCC (network-consistency-check)

Answer 23

Compares the layout netlist and the schematic netlist

Question 24

Parasitic extraction

Answer 24

Form of netlist extraction performed only on the layout

Included inferred capacitances from adjacent metal layers

Complex parasitic devices may exist (parasitic diodes, BJTs) which alter the behavior

Question 25

Final simulation

Answer 25

Core circuit’s netlist is simulated with parasitics to determine if adjustments need to be made

Question 26

Other ideas involved in EDA

Answer 26

Design-for-test

Design-for-manufacturing

Question 27

This EDA design flow is how we achieve reliability and yield even though

Answer 27

VLSI circuits have many nodes

VLSI circuits tend to be mass-manufactured

VLSI circuit components are micro or nanoscopic

Question 28

Thyristor

Answer 28

When of the transistors is turned on, the other one begins conducting too

The both keep each other in saturation until all the voltages in the system return to 0

Question 29

Latch-up

Answer 29

Can only be detected in parasitic simulation

Causes a DC short between power and ground

Can be triggered by:

• noise in power supply
• cosmic rays
• transients from RLC circuits

Discovered during simulation, extra layers for isolation are added where needed or the transients are mitigated