VLIW Theory Flashcards
What are the behaviors that the compiler cannot predict?
The cash and the branch behaviors
Can we have in the bundle more than one branch instruction?
No, we can’t
What are the requirements of the fetching stage on a multiple issue processor
Higher bandwidth from the instruction cache
How the decision of the instructions to be issued is taken any multiple issue processor
Either by dynamic scheduling or static scheduling
What are the bundles in a VLIW architecture?
They are a single issue packet that represents a wide instruction with multiple independent operations
What is the impact of the fact that in a VLIW architecture there is a shared multi ported register file
The implies in the necessity of having enough ports to read and write the multiple operations issued by each very long single instruction in parallel
Therefore, in the case of a 4 slot bundle we need eight read ports to read eight source registers and four write ports to write four destination register per cycle
What happens in case there is not enough parallelism in the source code to fill in the available operation slots
NOPs are inserted
What is the impact of the number of functional unities compared to the number of slots in the bundle, In the architecture
If each slot is assigned to functional unit the decode unit is a simple decoder otherwise, if there are more parallel functional units than the number of issues, the architecture must have a dispatch network to redirect each operation and the related source operands to the target FU
How does the VLIW processor solves RAW Hazard?
The compiler during the scheduling phase, reorders statically instructions (not involved in the dependency) otherwise the compiler introduces some NOPs
What information must be exposed to the compiler in order to obtain correct instruction execution?
Operation latencies and data dependencies must be exposed to the compiler
How are the WAR and WAW hazard solved in the VLIW processors
They are solved statically by the compiler by correctly selecting temporary slots for the operations or by using register renaming
How are Miss predicted branches solved in the VLIW architecture
A miss predicted branch must be solved dynamically by the hardware by flushing the execution of the speculative instruction in the pipeline
What needs to be done and what is the effect of avoiding structural hazards accessing the RF and WAR/WAW Hazard
It is necessary to keep in order execution, the write back phase of the parallel operations in a bundle must occur at the same clock cycle
This Implies that each bundle is constrained to the latency of the longer latency operation in it
What is the implication of doing out of order execution?
These way, we need to check in the write back phase for RF write accesses (avoid structural hazards) and WAR/WAW Hazzard
What is and what causes register pressure
Register pressure is related to the occupation of the registers
It is caused by the multicycle latency of the operations together with the multiple issue of instructions that generates an increment of the number of register occupied overtime
What are the events that the compiler at static time does not know about
Data cache misses and branch miss predictions
What are basic blocks?
Straight line code sequence with no branches in/out except at the entry/exit point
What is the relationship between basic blocks, data dependencies and the exploitable ILP in a program?
Beyond the fact that the amount of parallelism available within a basic block is small, data dependencies can further limit to the amount of ILP. We can exploit within a basic block.
Therefore, to obtain substantial performance enhancements, we must exploit ILP across multiple basic blocks
