VERILOG HDL: BASIC CONSTRUCTS AND CONVENTIONS PART 1 Flashcards

VERILOG HDL: BASIC CONSTRUCTS AND CONVENTIONS PART 1

1
Q

a designer must use a ____ design methodology to do efficient Verilog HDL–based design

A

good

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2
Q

____ and ____ design methodologies

A

top-down; bottom-up

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3
Q

top-down defines the ____ and identify ____

Top-Down Design Methodology

A

top-level block first; sub-blocks after

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4
Q

we further ____ the sub-blocks until we come to ____

Top-Down Design Methodology

A

subdivide; leaf cells

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5
Q

leaf cells are cells that ____

Top-Down Design Methodology

A

cannot further be divided

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6
Q

bottom-up identifies ____ and use these to ____ until we build the top-level block

Bottom-Up Design Methodology

A

building blocks first; create higher level blocks

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7
Q

a ____ flows is used typically

Design Methodologies

A

combination of top-down and bottom-up

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8
Q

____ define the specifications of the top-level block

A

design architects

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9
Q

____ break up the functionality into blocks and sub-blocks

A

logic designers

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10
Q

____ are designing optimized circuits for leaf-level cells, they build high-level cells by using these leaf-level cells

A

circuit designers

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11
Q

____ is the basic building block in Verilog

A

Module

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12
Q

a module provides necessary functionality through its ____

A

port interface

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13
Q

____ are where we interact with the module

A

Ports

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14
Q

ports can be ____

A

inputs, outputs, or bi-directional

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15
Q

____ is a process of creating an instance from module

A

module instantiation

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16
Q

each instance must be given a ____

Modules and Ports

A

unique name

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17
Q

____ are illegal (module definition inside a module)

A

nested modules

18
Q
  • user-specified name of Verilog objects
  • it can be a name for module, wire, variable, function, event
A

Identifiers

19
Q
  • predefined identifiers
  • have special meaning in Verilog
20
Q

whitespace characters are ____, except when they serve to ____

Verilog Syntax

A

ignored; separate identifiers

21
Q

____ precedes the operand, e.g., ~A or !A

Valid Operators

22
Q

____ appear between two operands, e.g., A+B or A&B

Valid Operators

23
Q

____ have two separate operators and three separate operands e.g., EN ? X : Z

Valid Operators

24
Q

A ____ is a sequence of characters that are enclosed by double quotes

25
Nets represents the ____
connections between hardware elements
26
Nets have ____ on them by the outputs of devices that they are connected to
values continuously driven
27
* declared using the keyword wire * by default, size is 1-bit (scalar) and value is Z
Nets
28
Registers represent ____
data storage elements
29
Registers ____ until another value is placed onto them
retain value
30
____ registers with hardware registers (built from flip-flops)
do not confuse
31
a register does not need a ____
driver
32
* by default, size is 1-bit (scalar) and value is x * declared using the keyword reg
Registers
33
Nets and registers data types can be declared as ____
multiple bit-widths
34
____ are added to define bit size of a vector
square brackets
35
the left number in the square brackets is always the ____ of the vector
most significant bit
36
it is possible to address bits or parts of vectors, this is called ____
part-select of bit select
37
____ is a general-purpose register data type used for manipulating quantities such as counting
Integer
38
____ is specified in decimal notation (e.g., 3.14) or in scientific notation (e.g., 3e6, which is 3 x 10^6)
Real
39
____ is a special time register data type to store simulation time
Time
40
____ is your Verilog code that describes the circuit
design block
41
____ a.k.a testbench perform simulations and tests on your design block
stimulus block