unit 6 single-Cycle Processor: Daatpath Flashcards

covers 7.1 7.2 and 7.3 of the Sarah Harris and David Harris (2015) Digital Design and Computer Architecture - ARM Edition, Elsevier

1
Q

microarchitecture

A

the connection between logic and architecture. T

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2
Q

microarchitecture is the specific arrangement of

A

registers, ALUs, finite state machines(FSMs), memories, and other logic building blocks.

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3
Q

architectural state for the ARM processor consists of?

A

16 32-bit registers and the status register

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4
Q

what are ADD, SUB, AND, and ORR

A

data processing instructions

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5
Q

what are LDR and STR?

A

Memory instructions

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6
Q

B stands for?

A

branch

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7
Q

how do we divide our microarchitectures?

A

int two interacting parts: the datapath and the control unit

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8
Q

what does the data path operate on?

A

words of data

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9
Q

what does a datapath contain?

A

structures such as memories, registers, ALUs, and multiplexers

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10
Q

what is the size of the 32-bit ARM architecture’s datapath?

A

32-bit

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11
Q

where does the control unit receive instructions from?

A

the current instructions are received from the datapath

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12
Q

what does the control unit tell the datapath?

A

how to execute the instructions it receives

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13
Q

how does the control unit control the operation of the datapath?

A

it produces multiplexer select, register enable, and memory write signals

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14
Q

what are heavy lines used to indicate?

A

32-bit data busses

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15
Q

what are medium lines used to indicate?

A

narrower busses, such as 4 bit address busses on the register file

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16
Q

what do narrow lines indicate?

A

1-bit buses

17
Q

what do blue lines represent?

A

control signals, such as the register file write enable

18
Q

what does the program counter(PC) do?

A

it outputs points to the current instruction

19
Q

what is PC’?

A

its the input for PC and it indicates the address of the next instruction

20
Q

how many read ports does the instruction memory have?

A

a single read port. It takes a 32-bit instruction address input A, and reads the 32-bit data from that address on the read data out, RD

21
Q

what registers does the 15-element x 32-bit register file hold?

A

R0-R14 and has an additional input to receive R15 from the PC.

22
Q

what are the Register file ports?

A

two read ports and one write port

23
Q

what kind of input do the read ports take?

A

4-bit address inputs

24
Q

how many ports does the data memory have?

A

a single read/ write port

25
Q

if the write enable is 0 what happens?

A

it reads address A onto RD

26
Q

the instruction memory, register file, and data memory are all?

A

read combinationally, meaning if the address changes, then the new data appears at RD after some propagation delay; no clock is involved

27
Q

a single-cycle microarchitecture executes an entire instruction in?

A

one cycle

28
Q

a multicycle microarchitecture executes an entire instruction in?

A

a series of shorter cycles

29
Q

pipeline microarchitecture applies a_____ to____?

A

pipeline, to the single-cycle microarchitecture. executing multiple processes at the same time